Memory controller for packet applications
View Patent ↗A method and apparatus for accessing and storing data in a memory are disclosed. The system includes a memory controller coupled to a memory having locations characterized by banks and lines. The memory controller is configured for storing a data packet with data bursts in sequence in consecutive memory locations, while providing the capability of reading or writing data bursts out of sequence by accessing the consecutive memory locations in a random order.
1. A method of data access and storage, the method comprising:
(a) providing a memory having a number of locations characterized by M banks and N lines, where M and N are positive integers;
(b) providing a data packet having a plurality of data bursts;
(c) analyzing current statistics on latency in accessing ones of the M banks;
(d) determining a sequence to write the data bursts to memory based on the statistics; and
(e) writing the data bursts to a plurality of memory locations to store the data packet, wherein the data bursts are stored in respective ones of the M banks according to the determined sequence.
2. The method of claim 1 , further comprising:
(f) reading the data bursts from the plurality of consecutive memory locations.
3. The method of claim 2 , wherein at least one of steps (e) and (f) is performed by accessing the plurality of data bursts out of sequence from the first plurality of consecutive memory locations.
4. The method of claim 2 , wherein at least one of steps (e) and (f) is performed by accessing the plurality of data bursts in sequence from the first plurality of consecutive memory locations.
5. The method of claim 1 , wherein the memory is a dynamic random access memory (DRAM).
6. An apparatus, comprising:
a memory having memory locations characterized by banks and lines;
a memory controller coupled to the memory for storing and retrieving a data packet having a number of data bursts;
wherein the memory controller is configured to store the number of data bursts in sequence in a plurality of consecutive locations in the memory based on current statistics on latency in accessing the memory banks.
7. The apparatus of claim 6 , wherein the memory controller is further configured to access the plurality of consecutive memory locations to allow at least one of reading and writing the data bursts in an out-of-sequence manner.
8. The apparatus of claim 6 , wherein the memory controller is further configured to access the plurality of consecutive memory locations to allow at least one of reading and writing the data bursts in an in-sequence manner.
9. The apparatus of claim 6 , wherein the memory is a dynamic random access memory.
10. The apparatus of claim 6 , wherein the memory controller is provided in a traffic manager of a packet line card for telecommunication application.