Methods for synchronous code retrieval from an asynchronous source

1. A method for delivering code to a host system, the method comprising the steps of:

(a) accepting a CPU request for a code segment, from a host-system processor of the host system;

(b) initiating a retrieval process to retrieve said code segment;

(c) upon expiration of a predetermined time, checking whether said code segment is ready for delivery;

(d) upon said predetermined time expiring before said code segment is ready for delivery, providing a software interrupt (SWI) that is different than said code segment, wherein said SWI causes said host-system processor to disable hardware interrupts, store all CPU registers and statuses, and jump to a reset-vector address to initiate a reset-vector program; and

(e) upon said predetermined time expiring after said code segment is ready for delivery, providing said code segment.

2. The method of claim 1 , wherein a reset-vector code located at said reset-vector address, includes a command to request said code segment again.

3. The method of claim 1 , wherein the reset vector includes code that causes the host-system processor to execute program code in a finite loop.

4. The method of claim 1 , wherein the operations of disabling hardware interrupts, storing all CPU registers and statues, and jumping to a reset-vector address are performed in one CPU atomic operation.

5. The method of claim 1 , wherein after completion of the reset-vector program, the SWI causes said host-system processor to restore the CPU registers and statuses, enable the hardware interrupts, and jump back to the address that initiated the SWI.

6. The method of claim 5 , wherein the operations of restoring the CPU registers and statuses, enabling the hardware interrupts, and jumping back to the address that initiated the SWI are performed in one CPU atomic operation.

7. The method of claim 1 , wherein the method satisfies a synchronous CPU request for command code with code from an asynchronous source.

8. A method for satisfying synchronous requests for command code, the method comprising:

accepting a CPU request for a code segment from a host-system processor of the host system;

initiating a retrieval process to retrieve said code segment;

upon determining that said code segment can be delivered on time, then providing said code request;

upon determining that said code segment cannot be delivered on time, avoiding a situation of latency by providing the host-system processor with replacement code, the replacement code configured to cause said host-system processor, in one CPU atomic operation, to disable hardware interrupts, store all CPU registers and statuses, and jump to a reset-vector address to initiate a reset-vector program.

9. The method of claim 8 , wherein the reset-vector program defines a wait-in-loop program.

10. The method of claim 8 , wherein the replacement code is configured to cause said host-system processor, upon completion of the reset-vector program and in one CPU atomic operation, to restore the CPU registers and statuses, enable the hardware interrupts, and jump back to the address that initiated the replacement code.

11. The method of claim 8 , further comprising:

upon determining that the code segment has not loaded during the execution of the reset-vector program, then providing the host-system processor with replacement code again.

12. The method of claim 8 ,

wherein it is determined that said code segment can be delivered on time when said code segment is located in volatile memory; and

wherein it is determined that said code segment cannot be delivered on time when said code segment is located in non-volatile memory.