Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FET computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
1. A method for permuting data before the data is sent to local memories of processing elements (PEs) for inbound transfers or before being sent to system memories for outbound transfers comprising the steps of:
reordering data within data elements of a block of data elements in a direct memory access (DMA) controller; and
performing other stream oriented operations on said data elements including masking, data merging or complementing operations in the DMA controller to create a modified block of data elements.
2. The method of claim 1 wherein said step of data merging further comprises:
performing a logical AND operation with a mask followed by performing a logical OR operation with a constant.
3. The method of claim 1 wherein said step of complementing further comprises using a logical XOR operation with a specified mask.
4. The method of claim 1 wherein the steps of reordering and performing other stream, oriented operations are controlled by DMA instructions that are executed in the DMA controller.
5. The method of claim 1 wherein data elements of the modified block of data elements are sent to addresses as specified by the DMA controller.
6. The method of claim 1 wherein a modified data element of the modified block of data elements is sent to a multicast address specifying a parallel distribution of the modified data element to one or more PEs or one or more system memories.
7. The method of claim 1 further comprising:
generating for each PE a base plus index as a virtual offset into a PE local memory relative to address zero of the first location in each PE's local memory; and
translating a PE virtual ID to a physical ID to select a PE, wherein a virtual ID is assigned to support various data distribution and collection patterns, a physical ID is based on a physical placement of the PEs, and an address of a data element within the PE local memory is specified by the physical ID to select the PE local memory and the virtual offset to select the address within the PE local memory.
8. The method of claim 7 further comprising:
translating the virtual offset by an address permutation and selection mechanism to a physical offset.
9. The method of claim 7 wherein the translating a PE virtual ID to a physical ID includes use of a table that maps PE virtual IDs to PE physical IDs.
10. An apparatus for permuting data before the data is sent to local memories of processing elements (PEs) for inbound transfers or before being sent to system memories for outbound transfers, the apparatus comprising:
a transfer controller for reordering data within data elements of a block of data elements in a direct memory access (DMA) controller; and
logic circuits for performing other stream oriented operations on said data elements including masking, data merging or complementing operations under control of the DMA controller to create a modified block of data elements.
11. The apparatus of claim 10 wherein the logic circuits are associated with the transfer controller and provide the stream oriented operations on the data elements before being sent to each of the PE local memories.
12. The apparatus of claim 10 further comprising:
a plurality of local memory interface units (LMIUs), each LMIU coupled to a PE local memory and each LMIU coupled to the transfer controller over a DMA bus, each LMIU provides PE relative operations on data transferred over the DMA bus.
13. The apparatus of claim 12 , wherein the PE relative operations are determined in response to a PE's ID and a PE operation code specified by the transfer controller.
14. The apparatus of claim 13 , wherein the PE operation code is specified by a group of signals that is part of the DMA bus.
15. The apparatus of claim 13 , wherein the PE operation code is specified on a data bus that is part of the DMA bus and under control of a signal indicating whether the data bus contains the PE operation code or data.