Variable gain amplifier with wide gain variation and wide bandwidth

1. A variable gain amplifier, comprising:

a differential amplification unit amplifying and outputting a difference between a first input signal and a second input signal inputted via a first input terminal and a second input terminal, respectively, according to a first bias current of the first input terminal and second input terminal, to a first output terminal and a second output terminal;

a diode-connected load unit comprising loads diode-connected to the first output terminal and second output terminal, respectively, the loads receiving a second bias current; and

a gain control unit controlling a gain between the input terminals and the output terminals of the differential amplification unit by controlling the size of the first bias current and second bias current;

wherein the diode-connected load unit comprises:

a fifth n-channel metal-oxide semiconductor transistor having a drain connected to the first output terminal and a gate mutually connected to the drain; and

a sixth n-channel metal-oxide semiconductor transistor having a drain connected to the second output terminal and a gate mutually connected to the drain,

wherein sources of the fifth n-channel metal-oxide semiconductor transistor and sixth n-channel metal-oxide semiconductor transistor are connected to each other, and the second bias current is provided to the sources of the fifth and sixth n-channel metal-oxide semiconductor transistors.

2. The amplifier of claim 1 , wherein the differential amplification unit comprises:

a first n-channel metal-oxide semiconductor transistor having a gate connected to the first input terminal; and

a second n-channel metal-oxide semiconductor transistor having a gate connected to the second input terminal,

wherein sources of the first n-channel metal-oxide semiconductor transistor and second n-channel metal-oxide semiconductor transistor are connected to each other, and the first bias current is provided to the sources of the first and second n-channel metal-oxide semiconductor transistors.

3. The amplifier of claim 2 , wherein the differential amplification unit further comprises:

a third n-channel metal-oxide semiconductor transistor having a source connected to a drain of the first n-channel metal-oxide semiconductor transistor and a drain connected to the first output terminal; and

a fourth n-channel metal-oxide semiconductor transistor having a source connected to a drain of the second n-channel metal-oxide semiconductor transistor and a drain connected to the second output terminal,

wherein the third n-channel metal-oxide semiconductor transistor and fourth n-channel metal-oxide semiconductor transistor receive a predetermined bias voltage via gates thereof.

4. The amplifier of claim 3 , wherein the first through fourth n-channel metal-oxide semiconductor transistors have an identical width-to-length ratio.

5. The amplifier of claim 3 , wherein the gain control unit comprises:

a first current source connected between the sources of the first n-channel metal-oxide semiconductor transistor and second n-channel metal-oxide semiconductor transistor and a ground;

a seventh n-channel metal-oxide semiconductor transistor having a drain connected to the sources of the first n-channel metal-oxide semiconductor transistor and second n-channel metal-oxide semiconductor transistor and having a source connected to the ground;

a second current source connected between the sources of the fifth n-channel metal-oxide semiconductor transistor and sixth n-channel metal-oxide semiconductor transistor and the ground; and

an eighth n-channel metal-oxide semiconductor transistor having a drain connected to the sources of the fifth n-channel metal-oxide semiconductor transistor and sixth n-channel metal-oxide semiconductor transistor and having a source connected to the ground,

wherein a sum of the bias voltage and a variable control voltage is provided to a gate of the seventh n-channel metal-oxide semiconductor transistor,

a difference between the bias voltage and the control voltage is provided to a gate of the eighth n-channel metal-oxide semiconductor transistor, and

currents generated by the first current source and second current source have a size identical to each other.

6. The amplifier of claim 2 , wherein the first n-channel metal-oxide semiconductor transistor, second n-channel metal-oxide semiconductor transistor, fifth n-channel metal-oxide semiconductor transistor, and sixth n-channel metal-oxide semiconductor transistor have an identical width-to-length ratio.

7. The amplifier of claim 1 , further comprising a first active-inductive load and a second active-inductive load connected to the first output terminal and second output terminal, respectively.

8. The amplifier of claim 7 , wherein the first active-inductive load comprises:

a ninth n-channel metal-oxide semiconductor transistor having a drain connected to a supply voltage source and a gate connected to the first output terminal;

a first p-channel metal-oxide semiconductor transistor having a source connected to the supply voltage source, a drain connected to the first output terminal, and a gate connected to a source of the ninth n-channel metal-oxide semiconductor transistor;

a first capacitor connected between the source of the ninth n-channel metal-oxide semiconductor transistor and a ground; and

a third current source supplying a current to the source of the ninth n-channel metal-oxide semiconductor transistor.

9. The amplifier of claim 7 , wherein the second active-inductive load comprises:

a tenth n-channel metal-oxide semiconductor transistor having a drain connected to a supply voltage source and a gate connected to the second output terminal;

a second p-channel metal-oxide semiconductor transistor having a source connected to the supply voltage source, a drain connected to the second output terminal, and a gate connected to a source of the tenth n-channel metal-oxide semiconductor transistor;

a second capacitor connected between the source of the tenth n-channel metal-oxide semiconductor transistor and a ground; and

a fourth current source supplying a current to the source of the tenth n-channel metal-oxide semiconductor transistor.

10. The amplifier of claim 5 , wherein the first current source and second current source generate a current decreased as temperature increases.

11. The amplifier according to claims 5 , wherein the first current source and second current source comprise:

a third p-channel metal-oxide semiconductor transistor having a source connected to a supply voltage;

a fourth p-channel metal-oxide semiconductor transistor having a source connected to the supply voltage and a gate and a drain connected to a gate of the third p-channel metal-oxide semiconductor transistor;

an eleventh n-channel metal-oxide semiconductor transistor having a gate and a drain connected to a drain of the third p-channel metal-oxide semiconductor transistor, and a source that is grounded;

a twelfth n-channel metal-oxide semiconductor transistor having a drain connected to the drain of the fourth p-channel metal-oxide semiconductor transistor and a gate connected to the gate of the eleventh n-channel metal-oxide semiconductor transistor;

a first resistor connected between a source of the twelfth n-channel metal-oxide semiconductor transistor and the ground and having a resistance value increasing as temperature increases;

a thirteenth n-channel metal-oxide semiconductor transistor having a gate connected to the gate of the eleventh n-channel metal-oxide semiconductor transistors, and a source that is grounded; and

a fourteenth n-channel metal-oxide semiconductor transistor having a gate connected to the gate of the eleventh n-channel metal-oxide semiconductor transistor, and a source that is grounded,

wherein drain currents of the thirteenth and fourteenth n-channel metal-oxide semiconductor transistors are provided as the current generated by the first current source and second current source.

12. The amplifier according to claim 5 , wherein the first current source and second current source comprise:

a temperature-independent current source generating a uniform current unchanged by a change in temperature;

a fifth p-channel metal-oxide semiconductor transistor having a source connected to a supply voltage;

a sixth p-channel metal-oxide semiconductor transistor having a source connected to the supply voltage, and a gate and a drain connected to a gate of the fifth p-channel metal-oxide semiconductor transistor;

a fifteenth n-channel metal-oxide semiconductor transistor having a gate and a drain connected to a drain of the fifth p-channel metal-oxide semiconductor transistor, and a source that is grounded;

a sixteenth n-channel metal-oxide semiconductor transistor having a drain connected to the drain of the sixth p-channel metal-oxide semiconductor transistor and a gate connected to the gate of the fifteenth n-channel metal-oxide semiconductor transistor;

a second resistor connected between a source of the sixteenth n-channel metal-oxide semiconductor transistor and the ground and having a resistance value decreasing as temperature increases;

a seventeenth n-channel metal-oxide semiconductor transistor receiving the current generated by the temperature-independent current source and having a gate connected to the gate of the fifteenth n-channel metal-oxide semiconductor transistor, and a source that is grounded;

an eighteenth n-channel metal-oxide semiconductor transistor having a drain and a gate connected to a drain of the seventeenth n-channel metal-oxide semiconductor transistor, and a source that is grounded;

a nineteenth n-channel metal-oxide semiconductor transistor having a gate connected to the gate of the eighteenth n-channel metal-oxide semiconductor transistor, and a source that is grounded; and

a twentieth n-channel metal-oxide semiconductor transistor having a gate connected to the gate of the eighteenth n-channel metal-oxide semiconductor transistor, and a source that is grounded,

wherein drain currents of the nineteenth and twentieth n-channel metal-oxide semiconductor transistors are provided as the current generated by the first current source and second current source.

13. A variable gain amplifier, comprising:

a differential amplification unit amplifying and outputting a difference between a first input signal and a second input signal inputted via a first input terminal and a second input terminal, respectively, according to a first bias current of the first input terminal and second input terminal, to a first output terminal and a second output terminal;

a diode-connected load unit comprising loads diode-connected to the first output terminal and second output terminal, respectively, the loads receiving a second bias current; and

a gain control unit controlling a gain between the input terminals and the output terminals of the differential amplification unit by controlling the size of the first bias current and second bias current;

wherein the differential amplification unit comprises:

a first n-channel metal-oxide semiconductor transistor having a gate connected to the first input terminal; and

a second n-channel metal-oxide semiconductor transistor having a gate connected to the second input terminal;

wherein sources of the first and second n-channel metal-oxide semiconductor transistors are connected to each other, and the first bias current is provided to the sources of the first and second n-channel metal-oxide semiconductor transistors;

wherein the differential amplification unit further comprises:

a third n-channel metal-oxide semiconductor transistor having a source connected to a drain of the first n-channel metal-oxide semiconductor transistor, and a drain connected to the first output terminal; and

a fourth n-channel metal-oxide semiconductor transistor having a source connected to a drain of the second n-channel metal-oxide semiconductor transistor, and a drain connected to the second output terminal,

wherein the third and fourth n-channel metal-oxide semiconductor transistors receive a predetermined bias voltage via gates thereof.

14. The amplifier of claim 13 , wherein the first through fourth n-channel metal-oxide semiconductor transistors have an identical width-to-length ratio.

15. A variable gain amplifier, comprising:

a differential amplification unit amplifying and outputting a difference between a first input signal and a second input signal inputted via a first input terminal and a second input terminal, respectively, according to a first bias current of the first input terminal and second input terminal, to a first output terminal and a second output terminal;

a diode-connected load unit comprising loads diode-connected to the first output terminal and second output terminal, respectively, the loads receiving a second bias current;

a gain control unit controlling a gain between the input terminals and the output terminals of the differential amplification unit by controlling the size of the first bias current and second bias current; and

a first active-inductive load and a second active-inductive load connected to the first output terminal and second output terminal, respectively;

wherein the first active-inductive load comprises:

a ninth n-channel metal-oxide semiconductor transistor having a drain connected to a supply voltage and a gate connected to the first output terminal;

a first p-channel metal-oxide semiconductor transistor having a source connected to the supply voltage, a drain connected to the first output terminal, and a gate connected to a source of the ninth n-channel metal-oxide semiconductor transistor;

a first capacitor connected between the source of the ninth n-channel metal-oxide semiconductor transistor and a ground; and

a third current source supplying a current to the source of the ninth n-channel metal-oxide semiconductor transistor.

16. A variable gain amplifier, comprising:

a differential amplification unit amplifying and outputting a difference between a first input signal and a second input signal inputted via a first input terminal and a second input terminal, respectively, according to a first bias current of the first input terminal and second input terminal, to a first output terminal and a second output terminal;

a diode-connected load unit comprising loads diode-connected to the first output terminal and second output terminal, respectively, the loads receiving a second bias current;

a gain control unit controlling a gain between the input terminals and the output terminals of the differential amplification unit by controlling the size of the first bias current and second bias current; and

a first active-inductive load and a second active-inductive load connected to the first output terminal and second output terminal, respectively;

wherein the second active-inductive load comprises:

a tenth n-channel metal-oxide semiconductor transistor having a drain connected to a supply voltage and a gate connected to the second output terminal;

a second p-channel metal-oxide semiconductor transistor having a source connected to the supply voltage, a drain connected to the second output terminal, and a gate connected to a source of the tenth n-channel metal-oxide semiconductor transistor;

a second capacitor connected between the source of the tenth n-channel metal-oxide semiconductor transistor and a ground; and

a fourth current source supplying a current to the source of the tenth n-channel metal-oxide semiconductor transistor.