Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics
View Patent ↗A processing system includes memory management software responsive to a translation lookaside buffer miss. The memory management software updates translation lookaside buffer information based on one or more missed virtual addresses. Entries of a first translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a first criterion. Entries of a second translation lookaside buffer are updated by the memory management software with information corresponding to the missed virtual addresses if memory page size information for the missed virtual addresses meet a second criterion. The first and second criterion may correspond to first and second memory page sizes supported by the respective translation lookaside buffers.
1. A method for managing memory of a processing system comprising at least one processor, the method comprising:
detecting, through the use of the at least one processor, a translation lookaside buffer miss;
identifying, through the use of the at least one processor, one or more missed virtual addresses corresponding to the translation lookaside buffer miss;
updating, through the use of the at least one processor, a first translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if memory page size information for the one or more missed virtual addresses corresponds to a first memory page size supported by the first translation lookaside buffer; and
updating, through the use of the at least one processor, a second translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if memory page size information for the one or more missed virtual addresses corresponds to a second memory page size supported by the second translation lookaside buffer, where the second memory page size is different than the first memory page size.
2. The method of claim 1 , where the second memory page size supported by the second translation lookaside buffer is larger than the first memory page size supported by the first translation lookaside buffer.
3. The method of claim 1 , further comprising consolidating page table entries that are contiguous to and inclusive of the one or more missed virtual addresses into one or more page table entries having a larger memory page size.
4. The method of claim 3 , further comprising using the consolidated page table entries to update either of the first or second translation lookaside buffer based on a value of the larger memory page size.
5. A processor comprising a physical memory having a software code embodied therein, the software code adapted to be executed to implement a method for managing memory of a processing system, the method comprising:
detecting a translation lookaside buffer miss;
identifying one or more missed virtual addresses corresponding to the translation lookaside buffer miss;
updating a first translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if memory page size information for the one or more missed virtual addresses corresponds to a first memory page size supported by the first translation lookaside buffer; and
updating a second translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if memory page size information for the one or more missed virtual addresses corresponds to a second memory page size supported by the second translation lookaside buffer, where the second memory page size is different than the first memory page size.
6. The storage medium of claim 5 , where the second memory page size supported by the second translation lookaside buffer is larger than the first memory page size supported by the first translation lookaside buffer.
7. The storage medium of claim 5 , further comprising consolidating page table entries that are contiguous to and inclusive of the one or more missed virtual addresses into one or more page table entries having a larger memory page size.
8. The storage medium of claim 7 , further comprising using the consolidated page table entries to update either of the first or second translation lookaside buffer based on a value of the larger memory page size.
9. A processing system comprising:
a physical memory comprising a page table and memory management software, where the page table includes a plurality of page table entries, where each of the plurality of page table entries includes memory page size information for a corresponding virtual address page;
a hardware module comprising a first translation lookaside buffer and a second translation lookaside buffer, where the first translation lookaside buffer is adapted to cache information for only page table entries having a first memory page size;
where the second translation lookaside buffer is adapted to cache information for only page table entries having a second memory page size, where the second memory page size differs from the first memory page size; and
where the memory management software is responsive to a translation lookaside buffer miss to update translation lookaside buffer information based on one or more missed virtual addresses, where the memory management software updates one or more entries of the first translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if memory page size information for the one or more missed virtual addresses corresponds to the first memory page size, and where the memory management software updates one or more entries of the second translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if the memory page size information for the one or more missed virtual address corresponds to the second memory page size.
10. The processing system of claim 9 , where the second memory page size is larger than the first memory page size.
11. The processing system of claim 9 , where the memory management software is further responsive to a translation lookaside buffer miss to consolidate page table entries that are contiguous to and inclusive of the one or more missed virtual addresses into one or more page table entries having a larger memory page size.
12. The processing system of claim 11 , where the memory management software updates either the first or the second translation lookaside buffer using information from the consolidated page table entries.
13. The processing system of claim 11 , where the larger memory page size corresponds to a largest memory page size to which the consolidated page table entries may be mapped.
14. The processing system of claim 9 , where the memory management software directly updates the one or more corresponding entries of the first and second translation lookaside buffers.
15. The processing system of claim 9 , where the memory management software indirectly updates the one or more corresponding entries of the first and second translation lookaside buffers through one or more further software modules.
16. The processing system of claim 9 , where the processing system comprises a single page table.
17. The processing system of claim 9 , where the processing system comprises multiple page tables.