Semiconductor with reduced pad pitch
View Patent ↗A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.
1. A semiconductor device comprising:
a first input/output buffer in a semiconductor chip;
a first pad arranged on the semiconductor chip over the first input/output buffer, when viewed in a vertical cross section, and designed to be used for bonding;
a second pad arranged on the semiconductor chip not over the first input/output buffer, when viewed in the vertical cross section, and designed to be used for both bonding and probing; and
a third pad arranged on the semiconductor chip not over the first input/output buffer, when viewed in the vertical cross section, and electrically connected to the first pad and designed to be used for probing.
2. The semiconductor device according to claim 1 , wherein the first pad is arranged on an inner position of the semiconductor chip compared to the second pad and the third pad.
3. The semiconductor device according to claim 2 , wherein the first pad and the third pad are electrically connected to the first input/output buffer, and
the second pad is electrically connected to a second input/output buffer in the semiconductor chip spaced from the first input/output buffer.
4. The semiconductor device according to claim 1 , wherein an area of the third pad is smaller than an area of the first pad in area.
5. The semiconductor device according to claim 1 , wherein the first input/output buffer area includes a plurality of macro cells, and
the first pad is one of a plurality of first pads, and each of the plurality of macro cells is connected to more than two of the plurality of first pads.
6. A semiconductor device comprising:
a first input/output buffer in a semiconductor chip;
a first pad arranged on the semiconductor chip over the first input/output buffer, when viewed in a vertical cross section, and electrically connected to the first input/output buffer arranged on the semiconductor chip;
a second pad and electrically connected to a second input/output buffer and arranged on an outer position of the semiconductor chip compared to the first pad, the second pad not being over the first input/output buffer, when viewed in the vertical cross section, and not being directly electrically connected to the first input/output buffer; and
a third pad and electrically connected to the first input/output buffer and arranged on an outer position of the semiconductor chip compared to the first pad, the third pad not being over the first input/output buffer, when viewed in the vertical cross section.