Method of manufacturing a thin film transistor array panel
View Patent ↗The present invention provides a thin film transistor array panel comprising: an insulating substrate; a first signal line formed on the insulating substrate and extending in a first direction; a second signal line formed on the insulating substrate, extending in a second direction, and intersecting the first signal line; a thin film transistor connected to the first and second signal lines; a passivation layer formed on the second signal line and having a contact hole exposing a portion of the second signal line; and a pixel electrode formed on the passivation layer and connected to the thin film transistor through the contact hole, wherein the passivation layer is formed by coating an organic solution that includes an organic insulating material and a solvent including at least one of PGMEP, EEP, and nBA.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a first signal line on an insulating substrate, the first signal line extending in a first direction;
forming a second signal line on the insulating substrate, the second signal line extending in a second direction, and intersecting the first signal line;
connecting a thin film transistor to the first and second signal lines;
forming a passivation layer on the second signal line, the passivation layer having a contact hole exposing a portion of the second signal line; and
forming a pixel electrode on the passivation layer and connected to the thin film transistor through the contact hole,
wherein the forming the passivation layer includes coating an organic solution that includes an organic insulating material and a solvent including PGMEP, EEP, and nBA.
2. The method of claim 1 , wherein the content ratio of PGMEP:EEP:nBA in the solvent is 50 to 90:30 to 5:20 to 5.
3. The method of claim 1 , wherein the organic solution further includes a surfactant comprising at least one of silane F and fluoric S.
4. The method of claim 3 , wherein the content ratio of silane F:fluoric S in the surfactant is 500 to 1500:50 to 500.
5. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on an insulating substrate;
forming a gate insulating layer on the gate line;
forming a semiconductor layer on the gate insulating layer;
forming a data line on the semiconductor layer;
forming a passivation layer on the data line, the passivation layer having a contact hole exposing a portion of the data line; and
forming a pixel electrode on the passivation layer and connecting the pixel electrode to the exposed portion of the data line through the contact hole,
wherein the forming the passivation layer includes coating an organic solution that includes an organic insulating material and a solvent including PGMEP, EEP, and nBA.
6. The method of claim 5 , wherein the content ratio of PGMEP:EEP:nBA in the solvent is 50 to 90:30 to 5:20 to 5.
7. The method of claim 5 , wherein the organic solution further includes a surfactant comprising at least one of silane F and fluoric S.
8. The method of claim 7 , wherein the content ratio of silane F:fluoric S in the surfactant is 500 to 1500:50 to 500.