Facilitating a channel change between multiple multimedia data streams
View Patent ↗Techniques are provided for facilitating a channel change between multiple data streams. Such techniques provide for receiving and processing a first stream of data packets within a buffer. The method also includes receiving buffer control header with a data packet of a second stream. The buffer control header includes a buffer clearance indicator that indicates whether the second data stream request for the first data stream to be cleared from the buffer. Moreover, the method includes clearing the first data stream from the buffer based on the buffer clearance indicator. Furthermore, the method includes immediately processing the second stream through the buffer once the first stream is cleared.
1. One or more computer-readable media having computer-useable instructions executable by a computing device for facilitating a channel change between multiple data streams, comprising:
receiving a first stream of data packets;
processing one or more data packets of the first stream within a buffer;
receiving a first data packet from a second stream of data packets related to multimedia content, the first data packet being a key frame with a buffer control header, wherein the buffer control header includes a buffer clearance indicator;
managing the one or more data packets based on the buffer clearance indicator; and
processing the second stream through the buffer to provide the related multimedia content to a user,
wherein managing the one or more data packets comprises continuing the processing of the one or more data packets until a minimum buffer size is reached for the second stream of data packets based on the clearance indicator.
2. The media according to claim 1 , further comprising clearing the one or more data packets from the buffer when the minimum buffer size is reached.
3. One or more computer-readable media having computer-useable instructions executable by a computing device for facilitating a channel change between multiple data streams, comprising:
receiving a first stream of data packets;
processing one or more data packets of the first stream within a buffer;
receiving a first data packet from a second stream of data packets related to multimedia content, the first data packet being a key frame with a buffer control header, wherein the buffer control header includes a buffer clearance indicator;
managing the one or more data packets based on the buffer clearance indicator; and
processing the second stream through the buffer to provide the related multimedia content to a user,
wherein managing the one or more data packets is further based on a clearability indicator of the first stream,
wherein managing the one or more data packets comprises comparing the buffer clearance indicator to the clearability indicator to determine whether to clear the one or more data packets from the buffer.
4. The media according to claim 3 , further comprising clearing the one or more data packets from the buffer if the clearability indicator indicates that the first stream is clearable and the buffer clearance indicator indicates that the second stream wants the buffer to cleared.
5. The media according to claim 3 , further comprising clearing the one or more data packets from the buffer if the second stream has a higher priority level than the first stream.
6. The media according to claim 3 , further comprising continuing the processing of the one or more data packets if the first stream has a higher priority level than the second stream.
7. A computing device, with a processor coupled to a memory, having a buffer control header for facilitating a channel change between multiple data streams, comprising:
the computing device processes an incoming data stream that has the buffer control header appended to each frame;
the computing device identifies a buffer clearance indicator located in the buffer control header, the buffer control header indicates if the incoming data stream wants a buffer to be cleared of previous data packets; and
the computing device identifies a clearability indicator located in the buffer control header, the clearability indicator indicates if a second data stream can cause the incoming data stream to be cleared from the buffer.
8. The computing device according to claim 7 , wherein the buffer clearance indicator includes a value for indicating that the previous data packets are to be cleared from the buffer.
9. The computing device according to claim 7 , wherein the buffer clearance indicator includes a value for indicating that the previous data packets are to be cleared from the buffer once a minimum buffer size is reached for the incoming data stream.
10. The computing device according to claim 7 , wherein the clearability indicator includes a value for indicating that the second data stream can clear the incoming data stream from the buffer if the second data stream desires.
11. The computing device according to claim 7 , wherein the clearability indicator includes a value for indicating that the second data stream can only clear the incoming data stream from the buffer if the second data stream has a higher priority level than the incoming data stream.
12. The computing device according to claim 7 , wherein the buffer control header is included with an In band Synchronization Header.
13. The computing device according to claim 7 , wherein a value for the minimum buffer size is included within a data packet of an incoming stream.
14. One or more tangible computer-readable media having computer-useable instructions executable by a computing device for facilitating a channel change between multiple data streams, comprising:
appending a buffer control header to at least one data packet of a data stream;
inputting a buffer clearance indicator and a clearability indicator into the buffer control header; and
transmitting the buffer control header with the clearance indicator and a clearability indicator to a client device.
15. The media according to claim 14 , wherein the at least one data packet includes a key frame.
16. The media according to claim 14 , wherein the buffer control header is included with an In Band Synchronization header.