Ballast control circuit for use with CCFL and EEFL lamps

1. A ballast control circuit for driving at least one gas discharge lamp comprises:

a high side driver operable to provide a high side driving signal to a high side switch of a half bridge controlled by the ballast control circuit, wherein the high side driving signal indicates a preferred duty cycle for the high side switch;

a low side driver operable to provide a low side driving signal to a low side switch of the half bridge, wherein the low side driving signal indicates a preferred duty cycle for the low side switch;

a dead time control circuit operable to provide a dead time signal that indicates a dead time during which both the high side and low side switches are turned OFF, wherein the dead time is set based on a value of an external dead time resistor; and

dimming circuitry operable to selectively dim the at least one gas discharge lamp, wherein the dimming circuitry dims the at least one gas discharge lamp based on a comparison between a dimming input and a voltage at a first timing pin of the ballast control circuit.

2. The ballast control circuit of claim 1 , wherein the duty cycle of the high side switch is adjusted via the high side driver while the dead time remains constant.

3. The ballast control circuit of claim 2 , wherein the voltage at the first timing pin changes based on a value of a first timing capacitor connected to the first timing pin.

4. The ballast control circuit of claim 3 , wherein the high side and low side switches are turned OFF when the dimming input is lower than the voltage at the first timing pin.

5. The ballast control circuit of claim 4 , wherein the duty cycle of the high side switch is maintained at a reduced level for a soft start period of time when the voltage at the first timing pin is less than the dimming input and the value of the dimming input is lower than a soft start threshold value.

6. The ballast control circuit of claim 5 , wherein the soft start threshold value is 1 volt and the soft start period of time is the time it takes for the voltage at the first timing pin to change from 0 volts to 1 volt.

7. A ballast control circuit for driving at least one gas discharge lamp comprises:

a high side driver operable to provide a high side driving signal to a high side switch of a half bridge controlled by the ballast control circuit, wherein the high side driving signal indicates a preferred duty cycle for the high side switch;

a low side driver operable to provide a low side driving signal to a low side switch of the half bridge, wherein the low side driving signal indicates a preferred duty cycle for the low side switch;

a dead time control circuit operable to provide a dead time signal that indicates a dead time during which both the high side and low side switches are turned OFF, wherein the dead time is set based on a value of an external dead time resistor; and

over current protection circuitry operable to turn the ballast control circuit OFF when a current sense input indicative of the current provided to the gas discharge lamp exceeds an over current threshold value for a predetermined period of time.

8. The ballast control circuit of claim 7 , wherein the predetermined period of time is based on a value of a second timing capacitor connected to a second timing pin.

9. The ballast control circuit of claim 8 , wherein the predetermined period of time ends when the voltage at the second timing pin exceeds a second threshold value.

10. The ballast control circuit of claim 9 , further comprising shut down circuitry operable to turn the ballast control circuit OFF when a lamp voltage signal indicative of a voltage provided across the gas discharge lamp exceeds a shut down threshold for the predetermined period of time.

11. The ballast control circuit of claim 10 , wherein the predetermined period of time is based on the voltage of the second timing capacitor connected to the second timing pin.

12. The ballast control circuit of claim 11 , where in the predetermined period of time ends when the voltage at the second timing pin exceeds a second threshold value.

13. The ballast control circuit of claim 2 , wherein the high side driver and the low side driver are driven at a maximum frequency for an ignition period of time at start up, such that the at least one gas discharge lamp is provided with a voltage sufficient to ignite the at least one gas discharge lamp.

14. The ballast control circuit of claim 13 , wherein the ignition period of time is based on the voltage at the first timing pin.

15. The ballast control circuit of claim 14 , wherein the voltage at the first timing pin changes based on a value of a first timing capacitor connected to the first timing pin.

16. The ballast control circuit of claim 15 , wherein the ballast control circuit is turned OFF after the ignition period when the at least one gas discharge lamp does not ignite.

17. The ballast control circuit of claim 16 , wherein the determination that the at least one gas discharge lamp has not ignited is based on a comparison of a lamp voltage signal indicative of the voltage across the at least one gas discharge lamp with an ignition value such that the at least one gas discharge lamp has ignited when the lamp voltage signal exceeds the ignition value.

18. The ballast control circuit of claim 17 , wherein the high side driver and the low side driver are driven at a minimum after the at least one gas discharge lamps is ignited.