Processing system having a supported page size information register
View Patent ↗A processing system includes initialization software that is executable by a processor to identify one or more memory page sizes supported by the processing system. The supported memory page sizes that are identified by the initialization software are stored in one or more memory page size identification registers. Individual bits of the one or more memory page size identification registers may be respectively associated with a memory page size. Whether a memory page size is supported by the processing system may be determined by checking the logic state of the individual bit corresponding to the memory page size.
1. A method for managing memory of a processing system comprising:
identifying memory page sizes supported by a processing system;
storing the identified memory page sizes in at least one memory page size identification register;
detecting a change in a page table including a plurality of page table entries, where each of the plurality of page table entries includes information for translating a virtual address to a corresponding physical address, memory page size for a corresponding virtual address page, and access permission information for the corresponding virtual address page;
responding to the detection by identifying contiguous page table entries having substantially the same access permission information;
analyzing the identified contiguous page table entries to determine whether a change of the memory page size for any of the identified contiguous page table entries is warranted, where the change of the memory page size corresponds to a supported page size as identified in the at least one memory page size identification register;
updating the memory page size information for at least one of the identified contiguous page table entries with new memory page size information if the analysis of the identified contiguous page table entries determines that a change of the memory page size of any of the identified contiguous page table entries is warranted, where the new memory page size information corresponds to a largest memory page size to which any of the identified contiguous page table entries may be mapped and which is supported by the processing system as identified in the at least one memory page size identification register; and
updating one or more entries of the translation lookaside buffer corresponding to at least one of the identified contiguous page table entries with the new memory page size information.
2. The method of claim 1 , where storing identified memory page sizes comprises setting bits corresponding to the supported memory page sizes in the at least one memory page size identification register.
3. A processing system comprising:
a processor;
initialization software executable by the processor to identify one or more supported memory page sizes for storage in one or more memory page size identification registers;
a page table including a plurality of page table entries, where each of the plurality of page table entries includes memory page size information for a corresponding virtual address page that is derived from the one or more memory page size registers;
a translation lookaside buffer adapted to cache information about a plurality of the page table entries including corresponding memory page size information; and
memory management software responsive to changes in the page table to consolidate contiguous page table entries into one or more page table entries having a larger memory page size identified as being supported in the one or more memory page size registers, where the memory management software further updates entries of the translation lookaside buffer corresponding to the consolidated contiguous page table entries; and
where the memory management software limits checking for contiguous page table entries to page table entries that are locally proximate page table entries that have been changed in the page table, deleted from the page table, and/or added to the page table, where the change, deletion, and/or addition corresponds to the change in the page table to which the memory management software has responded to make the check.
4. The processing system of claim 3 , where individual bits of the one or more memory page size identification registers are respectively associated with a memory page size, and where the one or more memory page size identification registers indicate that a memory page size is supported when the individual bit corresponding to the memory page size is set to a predetermined logic state.
5. The processing system of claim 3 , where the initialization software is further executable to initialize memory space.
6. The processing system of claim 3 , where the memory management software consolidates contiguous page table entries based on access permissions for the contiguous page table entries.
7. The processing system of claim 3 , where the memory management software consolidates contiguous page table entries based on memory boundary conditions for the contiguous page table entries.
8. The processing system of claim 3 , where the initialization software is executable by the processor to initialize the translation lookaside buffer.
9. Memory management system comprising:
a processor
initialization software executable by the processor to identify one or more supported memory page sizes for storage in one or more memory page size identification registers;
page table management software adapted to manage a page table including a plurality of page table entries, where each of the plurality of page table entries includes memory page size information for a corresponding virtual address page that is derived from the one or more memory page size identification registers;
translation lookaside buffer management software adapted to manage a translation lookaside buffer, where the translation lookaside buffer is adapted to cache information corresponding to a plurality of the page table entries including corresponding memory page size information; and
memory page size management software responsive to changes in the page table to consolidate contiguous page table entries into one or more page table entries having a larger memory page size that is identified as being supported by the one or more memory page size identification registers, where the memory page size management software further updates entries of the translation lookaside buffer corresponding to the consolidated contiguous page table entries;
where the memory management software limits checking for contiguous page table entries to page table entries that are locally proximate page table entries that have been changed in the page table, deleted from the page table, and/or added to the page table, where the change, deletion, and/or addition corresponds to the change in the page table to which the memory management software has responded to make the check.
10. The memory management system of claim 9 , where individual bits of the one or more memory page size identification registers are respectively associated with a memory page size, and where the one or more memory page size identification registers indicate that a memory page size is supported when the individual bit corresponding to the memory page size is set to a predetermined logic state.
11. The memory management system of claim 9 , where the initialization software is further adapted to initialize the translation lookaside buffer.
12. The memory management system of claim 9 , where the initialization software is further adapted to initialize system memory storage.
13. The memory management system of claim 9 , where the memory page size management software consolidates contiguous page table entries based on access permissions for the contiguous page table entries.
14. The memory management system of claim 9 , where the memory management software consolidates contiguous page table entries based on memory boundary conditions for the contiguous page table entries.
15. A storage medium comprising software code adapted to execute a method for managing memory of a processing system, where the method comprises:
identifying memory page sizes supported by a processing system;
storing the identified memory page sizes in at least one memory page size identification register;
detecting a change in a page table including a plurality of page table entries, where each of the plurality of page table entries includes information for translating a virtual address to a corresponding physical address, memory page size for a corresponding virtual address page, and access permission information for the corresponding virtual address page;
responding to the detection by identifying contiguous page table entries having substantially the same access permission information;
analyzing the identified contiguous page table entries to determine whether a change of the memory page size for any of the identified contiguous page table entries is warranted, where the memory page size corresponds to a supported page size as identified in the at least one memory page size identification register;
updating the memory page size information for at least one of the identified contiguous page table entries with new memory page size information if the analysis of the identified contiguous page table entries determines that a change of the memory page size of any of the identified contiguous page table entries is warranted, where the new memory page size information corresponds to a largest memory page size to which any of the identified contiguous page table entries may be mapped and which is supported by the processing system as identified in the at least one memory page size identification register; and
updating one or more entries of the translation lookaside buffer corresponding to at least one of the identified contiguous page table entries with the new memory page size information.
16. The storage medium of claim 15 , where storing identified memory page sizes comprises setting bits corresponding to the supported memory page sizes in the at least one memory page size identification register.