IP Library Granted Patent US 8,077,644
Granted Patent B2
US 8,077,644 · App. 11/780,604 · Granted Dec 13, 2011

Data transfer in a computing device

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Quick Facts
Patent No.
US 8,077,644
App. No.
11/780,604
Granted
Dec 13, 2011
Kind
B2
Abstract

A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.

Claims (89)

1. A computing device, comprising:

a hardware data processing unit comprising:

at least one data buffer comprising at least one logical input buffer and at least one logical output buffer; and

a hardware data transfer unit; and

a software control unit configured to process a data frame,

wherein the at least one logical input buffer contains the data frame, and the hardware data transfer unit is configured to transfer a first part of the data frame from the logical input buffer to the at least one logical output buffer, and

wherein the software control unit is configured to read the first part of the data frame from a logical output buffer, and to control the further transfer operations of the hardware data transfer unit based on information contained in the first part of the data frame.

2. The computing device according to claim 1 , wherein the software control unit is configured to control the further transfer operations of the hardware data transfer unit on a second part of the data frame based on information contained in the first part of the data frame.

3. The computing device according to claim 2 , wherein the second part of the data frame is at least the remaining part of the data frame.

4. The computing device according to claim 1 , wherein the at least one data buffer is a shared buffer.

5. The computing device according to claim 1 , wherein the at least one logical input buffer and the at least one logical output buffer are mapped to at least one data buffer.

6. The computing device of claim 1 , wherein the computing device is a communication device.

7. The computing device of claim 6 , wherein the communication device is a mobile communication device.

8. The computing device of claim 7 ,

wherein the communication device is configured to communicate according to a communication protocol, and

wherein the data frames comprise sub-layer data of a layer of the communication protocol, the first part of the data frame comprising header data of the sub-layer data, and a second part of the data frame comprising at least payload data of the sub-layer data.

9. The computing device of claim 8 , wherein the hardware data transfer unit is configured to:

detect sub-layer data in the at least one input buffer,

copy at least the header data of the sub-layer of a layer from the logical input buffer into the logical output buffer, and

inform the software control unit about the detected and copied sub-layer data.

10. The computing device of claim 1 , wherein the hardware data transfer unit is configured to perform the transfer of the first part of the data frame according to a pre-configuration.

11. The computing device of claim 1 , wherein the hardware data transfer unit is micro programmable.

12. The computing device of claim 6 ,

wherein the payload data of the sub-layer data contains header data and payload data of a higher sub-layer, and

wherein the hardware data transfer unit is configured to:

move the header data of the higher sub-layer data into a second logical output buffer according to the control information of the software control unit, and

move the payload data of the higher sub-layer data into a third logical output buffer according to the control information of the software control unit.

13. The computing device of claim 11 , wherein the third logical output buffer is an external memory.

14. The computing device of claim 1 , wherein the hardware data processing unit further comprises a cipher unit.

15. The computing device of claim 14 , wherein the cipher unit is configured to cipher and/or decipher data during and/or after the data transfer.

16. The computing device of claim 14 , wherein the software control unit is further configured to control the cipher unit.

17. The computing device of claim 1 , wherein the software control unit is further configured to manage the memory allocation and deallocation.

18. The computing device of claim 1 , wherein the software control unit is further configured to configure and pre-configure the data transfer unit.

19. The computing device of claim 1 , wherein the software control unit is further configured to send micro programs to the data transfer unit and/or the cipher unit.

20. The computing device of claim 8 , wherein the layer is the data link layer of a communication protocol.

21. A hardware data transfer unit, comprising:

a data moving unit configured to:

move a first part of a data frame from a logical input buffer to a logical output buffer, and

move a second part of the data frame according to control information of a software control unit; and

a control receive unit configured to receive the control information from the software control unit, the control information being based on the information contained in the transferred first part of the data frame.

22. The hardware data transfer unit of claim 21 , wherein the second part of the data frame contains at least the remaining part of the data frame.

23. The hardware data transfer unit of claim 21 , wherein the data frame comprises sub-layer data of a higher sub-layer according to a communication protocol, the first part of the data frame comprising header data of the sub-layer data, and a second part of the data frame comprising at least payload data of the sub-layer data.

24. The hardware data transfer unit of claim 21 further comprising:

a detection unit configured to detect sub-layer data in the logical input buffer;

a copy unit configured to copy at least the header data of the sub-layer of a layer from the logical input buffer into a first logical output buffer; and

a control send unit configured to inform the software control unit about the sub-layer data.

25. The hardware data transfer unit claim 21 , wherein the data moving unit is configured to perform the transfer of the first part of the data frame according to a pre-configuration.

26. The hardware data transfer unit claim 21 , wherein the hardware data transfer unit is micro programmable.

27. The hardware data transfer unit claim 23 , wherein the hardware data transfer unit is configured to:

move the header data of the higher sub-layer data into a second logical output buffer according to the control information of the software control unit, and

move the payload data of the higher sub-layer data into a third logical output buffer according to the control information of the software control unit.

28. The hardware data transfer unit of claim 24 , wherein the layer is the data link layer of a communication protocol.

29. A software control unit configured to receive a first part of a data frame from a hardware data transfer unit, to generate control information based on the data of the first part of the data frame, and to send the control information to the hardware data transfer unit for processing a second part of the data frame, wherein the control information for processing the second part of the data frame comprises:

disassemble-information for frame disassembling; and

transfer information for transferring the data frame from a logical input buffer to at least one logical output buffer.

30. The software control unit of claim 29 , wherein the second part of the data frame contains at least the remaining part of the data frame.

31. The software control unit of claim 29 , being further configured to configure and pre-configure the hardware data transfer unit.

32. The software control unit of claim 29 , being further configured to control a cipher unit configured to cipher and/or decipher data contained in the data frame.

33. The software control unit of claim 32 , being further configured to send micro programs to the hardware data transfer unit and/or to the cipher unit.

34. The software control unit of claim 33 , being further configured to control the cipher unit to cipher and/or decipher data during and/or after data transfer.

35. The software control unit of claim 29 , wherein the data frame is a frame of the data link layer of a communication protocol.

36. The software control unit of claim 29 , being further configured to manage memory allocation and de-allocation.

37. A method for performing a data transfer in a computing device, comprising:

transferring a first part of a data frame from a logical input buffer to a logical output buffer in a hardware data transfer unit;

receiving the first part of the data frame from the logical output buffer at a software control unit;

analyzing the information included the first part of the data frame in the software control unit;

sending control information according to the information in the first part of the data frame from the software control unit to the data transfer unit; and

transferring the data of a second part of the data frame to at least one logical output buffer according to the control information of the software control unit in the hardware transfer unit.

38. The method of claim 37 , further comprising performing, by the hardware data transfer unit, the transfer of the first part of the data frame according to a pre-configuration.

39. The method of claim 37 , wherein the second part of the data frame comprises at least the remaining part of the data frame.

40. The method of claim 37 , wherein the computing device communicates according to a communication protocol.

41. The method of claim 40 ,

wherein the logical input buffer contains sub-layer data of a layer of the communication protocol, and

wherein the method further comprises:

disassembling, by the hardware data transfer unit, the sub-layer data of a layer at least into higher sub-layer data units; and

moving, by the hardware data transfer unit, the disassembled data into a plurality of logical output buffers.

42. The method of claim 41 , further comprising:

detecting sub-layer data in the logical input buffer by the hardware data transfer unit;

copying at least the header data of the sub-layer of a layer from the logical input buffer into a first logical output buffer of the plurality of logical output buffers; and

informing the software control unit about the detected and copied sub-layer data.

43. The method of claim 42 , further comprising:

moving, by the hardware data transfer unit, the header data of the higher sub-layer data units into a second logical output buffer according to the control information of the software control unit; and

moving, by the hardware data transfer unit, the payload data of the higher sub-layer data into a third logical output buffer according to the control information of the software control unit.

44. The method of claim 41 , wherein the layer is the data link layer of a communication protocol.

45. The method of claim 37 , further comprising configuring and pre-configuring the data transfer unit by the software control unit.

46. The method of claim 37 , further comprising managing the memory allocation and deallocation by the software control unit.

47. The method of claim 37 , further comprising controlling, by the software control unit, a cipher unit for ciphering and/or deciphering data contained in the data frame.

48. The method of claim 47 , further comprising controlling, by the software control unit, the cipher unit to cipher and/or decipher data during and/or after the data transfer.

49. The method of claim 37 , further comprising sending, by the software control unit, micro programs to the hardware data transfer unit and/or the cipher unit.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053518/0586 →
CONFIRMATORY ASSIGNMENT EFFECTIVE AS OF JANUARY 1, 2018 Recorded Aug 12, 2020
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 053477/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →