Enhancement mode GaN FET with piezoelectric gate
View Patent ↗One or more enhancement mode GaN devices has a stress-reduced gate region which interrupts the normally conductive 2Deg layer. A piezoelectric film is disposed over the stress-reduced gate region and can be excited to deflect and apply a stress to the stress reduced gate region to reintroduce the conductive 2Deg layer in that region and to turn on the device. A depletion mode segment may also be provided.
1. An enhancement mode GaN FET comprising:
a substrate;
a buffer layer atop said substrate;
a GaN layer atop said buffer layer;
an AlGaN layer atop said GaN layer to define a conductive 2Deg layer at their interface;
an opening in said AlGaN layer to remove the strain which defines the electron gas of said 2Deg layer at the bottom of said opening;
a piezoelectric gate disposed in said opening for controllably applying a strain to the unstrained portion of said 2Deg layer adjacent said opening;
and source and drain electrodes atop said AlGaN layer and on opposite sides of said opening.
2. The device of claim 1 , wherein said opening extends only partially from the top of said AlGaN layer, leaving a thin web of AlGaN atop said GaN layer.
3. The device of claim 1 , wherein said piezoelectric gate comprises a thin film having a gate electrode on its top surface.
4. The device of claim 2 , wherein said piezoelectric gate comprises a thin film having a gate electrode on its top surface.
5. The process of operating a GaN FET in the enhancement mode, comprising the removal of stress from a selected region of its 2Deg layer to interrupt conduction of current through said 2Deg layer and applying a mechanical stress to said selected region to reestablish the 2Deg layer in said selected region.
6. The process of claim 5 , which includes a piezoelectric film disposed over said selected region for applying said mechanical stress and gate means on said piezoelectric film to cause said film to deflect to produce said mechanical stress in response to the application of a gate voltage to said gate.
7. The enhancement mode GaN FET of claim 1 , which further includes a termination region surrounding said FET to prevent parallel conduction of current through the 2Deg layer external to said enhancement mode GaN FET.
8. The enhancement mode GaN FET of claim 2 , which further includes a termination region surrounding said FET to prevent parallel conduction of current through the 2Deg layer external to said enhancement mode GaN FET.
9. The enhancement mode GaN FET of claim 4 , which further includes a termination region surrounding said FET to prevent parallel conduction of current through the 2Deg layer external to said enhancement mode GaN FET.
10. The enhancement mode GaN FET of claim 1 , which further includes at least a second identical GaN FET laterally displaced from said GaN FET and connected in a parallel therewith to increase channel width.
11. The device of claim 10 , which further includes a termination region surrounding each of said FETs to prevent parallel conduction of current through the 2Deg layer external to each of said FETs.
12. The enhancement mode FET of claim 1 , which further includes at least one depletion mode FET formed in said GaN layer and said AlGaN layer which depletion mode FET is laterally displaced from said enhancement mode FET.
13. The enhancement mode FET of claim 7 , which further includes at least one depletion mode FET formed in said GaN layer and said AlGaN layer which depletion mode FET is laterally displaced from said enhancement mode FET.
14. The enhancement mode FET of claim 10 , which further includes at least one depletion mode FET formed in said GaN layer and said AlGaN layer which depletion mode FET is laterally displaced from said enhancement mode FET.
15. The enhancement mode FET of claim 11 , which further includes at least one depletion mode FET formed in said GaN layer and said AlGaN layer which depletion mode FET is laterally displaced from said enhancement mode FET.