Level-shift circuit utilizing a single level-shift switch
View Patent ↗A level-shift circuit for use with a half bridge in accordance with an embodiment of the present application includes an oscillator operable to provide a timing signal, a level-shift switch controlled by the timing signal of the oscillator, a high side control circuit operable to provide a high side control signal to a high side switch of the half bridge to control the high side switch and a low side control circuit operable to provide a low side control signal to a low side switch of the half bridge to control the low side switch. The level-shift switch is turned ON when the timing signal is high such that the level-shift switch connects the high side control circuit to ground and the high side control signal stays low to keep the high side switch OFF when the timing signal is high. The low side control circuit provides the low side control signal to turn the low side switch ON a predetermined period of time after the timing signal goes high.
1. A level-shift circuit for use in a voltage conversion circuit utilizing a half bridge comprises:
an oscillator operable to provide a timing signal;
a level-shift switch controlled by the timing signal of the oscillator;
a high side control circuit operable to provide a high side control signal to a high side switch of the half bridge to control the high side switch; and
a low side control circuit operable to provide a low side control signal to a low side switch of the half bridge to control the low side switch; wherein
the level-shift switch is turned ON when the timing signal is high such that the level-shift switch connects the high side control circuit to ground and the high side control signal stays low to keep the high side switch OFF when the timing signal is high; and wherein
the low side control circuit provides the low side control signal to turn the low side switch ON a predetermined period of time after the timing signal goes high.
2. The level-shift circuit of claim 1 , wherein the low side control circuit further comprises:
a low side driver circuit operable to generate the low side control signal; and
a low side dead time circuit operable to provide a low side dead time signal to the low side driver circuit to delay an ON time of the low side switch indicated by the low side control signal for the predetermined period of time.
3. The level-shift circuit of claim 2 , wherein the low side dead time signal is a ramp signal and wherein the ON time of the low side switch indicated by the low side control signal is delayed until the low side dead time ramp signal reaches a predetermined threshold level.
4. The level-shift circuit of claim 3 , wherein the high side control circuit further comprises:
a high side driver circuit operable to generate the high side control signal; and
a high side dead time circuit operable to provide a high side dead time signal to the high side driver circuit to delay an ON time of the high side switch indicated by the high side control signal when the timing signal goes low, wherein the ON time of the high side switch is delayed for the predetermined period of time after the high timing signal goes low.
5. The level-shift circuit of claim 4 , wherein the high side dead time signal is a second ramp signal and wherein the ON time of the high side switch indicated by the high side control signal is delayed until the high side dead time ramp signal reaches the predetermined threshold level.
6. The level-shift circuit of claim 5 , wherein an input voltage at an input of the high side dead time circuit is pulled to ground when the level-shift switch is ON such that the input voltage to the high side dead time circuit remains at least a fixed amount lower than a supply voltage of the high side control circuit to ensure that the high side control signal keeps the high side switch OFF while the level-shift switch is ON.
7. The level-shifting circuit of claim 6 , further comprising a diode connected between the input of the high side dead time circuit and the supply voltage of the high side control circuit, wherein the diode sets the fixed amount that the input voltage stays below the supply voltage.
8. The level-shift circuit to claim 7 , further comprising a pull up resistor connected between the input to the high side dead time circuit and the supply voltage and in parallel with the diode, such that when the level-shift switch is OFF, the input voltage at the high side dead time circuit is pulled up to the supply voltage via the pull up resistor, such that the high side control signal will go high to turn the high side switch ON after the predetermined period of time.
9. The level-shift circuit of claim 8 , wherein the low side switch, the high side switch and the level-shift switch are implemented as metal-oxide-semiconductor field-effect transistors.
10. The level-shift circuit of claim 8 , wherein the low side switch, the high side switch and the level-shift switch are implemented as insulated gate bipolar transistors.
11. The level-shift circuit of claim 9 , wherein an output voltage is provided at a node between the high side switch and the low side switch and is provided to a load, and wherein the high side and low side switches are turned on and off based on the high side control signal and low side control signal, respectively, to control the output voltage.