IP Library Granted Patent US 7,436,344
Granted Patent B2
US 7,436,344 · App. 11/781,976 · Granted Oct 14, 2008

Pipeline A/D converter

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Quick Facts
Patent No.
US 7,436,344
App. No.
11/781,976
Granted
Oct 14, 2008
Kind
B2
Abstract

The present invention provides a pipeline A/D converter having resolution, allowable conversion processing rate and power consumption satisfying the requests of a system incorporating the pipeline A/D converter. The pipeline A/D converter in accordance with the present invention comprises a control section for outputting a control signal according to the operation state of an apparatus incorporating the pipeline A/D converter, and a pipeline A/D conversion section, the resolution and/or allowable conversion processing rate of which are switched by switching the capacitance in a built-in operational amplifier according to the control signal.

Claims (21)

1. A pipeline A/D converter having a first mode and a second mode and comprising multiple stages connected by pipelines, at least one of said stages comprising:

an amplifier,

a first pair of a first capacitor and a second capacitor, and

a second pair of a third capacitor and a fourth capacitor, wherein

in said first mode, said amplifier amplifies an analog input signal at the amplification factor corresponding to the capacitance of said first pair of capacitors and outputs an amplified signal, and in said second mode, said amplifier amplifies said analog input signal at the amplification factor corresponding to the capacitance of only said second pair of capacitors or the capacitance of said first and second pairs of capacitors and outputs an amplified signal, and wherein at least one of said stages comprises:

an amplifier;

a first pair of a first capacitor and a second capacitor connected in series, at least said first capacitor being charged with the charge corresponding to said analog input signal in a first period, the charges stored in said first capacitor and said second capacitor being redistributed in a second period while current flowing is prevented at the connection point of said first capacitor and said second capacitor, the connection point of said first capacitor and said second capacitor being connected to the input terminal of said amplifier, and one terminal of said second capacitor, not connected to said first capacitor, being connected to the output terminal of said amplifier; and

a second pair of a third capacitor and a fourth capacitor connected in series, at least said third capacitor being charged with the charge corresponding to said analog input signal in said first period, the charges stored in said third capacitor and said fourth capacitor being redistributed in said second period while current flowing is prevented at the connection point of said third capacitor and said fourth capacitor, the connection point of said third capacitor and said fourth capacitor being connected to an input terminal of said amplifier, and one terminal of said fourth capacitor, not connected to said third capacitor, being connected to an output terminal of said amplifier.

2. A The pipeline A/D converter in accordance with claim 1 , wherein said stage further comprises:

a first switch, one terminal of which receives said analog input signal and the other terminal of which is connected to one terminal of said first capacitor, not connected to said second capacitor, and said switch being turned ON in said first period and turned OFF in said second period;

a second switch, one terminal of which is connected to the connection point of said first switch and said first capacitor, said switch being turned OFF in said first period and turned ON in said second period, and at least the potential at the other terminal of said first capacitor being input to said amplifier;

a third switch, one terminal of which receives a DC bias voltage and the other terminal of which is connected to the connection point of said first capacitor and said second capacitor, and said switch being turned ON in said first period and turned OFF in said second period;

a fourth switch, one terminal of which receives said analog input signal or said DC bias voltage and the other terminal of which is connected to one terminal of said second capacitor, not connected to said first capacitor, and said switch being turned ON in said first period and turned OFF in said second period;

a fifth switch, one terminal of which is connected to the connection point of said second capacitor and said fourth switch and the other terminal of which is connected to the output terminal of said amplifier, and said switch being turned OFF in said first period and turned ON in said second period;

a sixth switch, one terminal of which receives said analog input signal and the other terminal of which is connected to one terminal of said third capacitor, not connected to said fourth capacitor, and said switch being turned ON in said first period and turned OFF in said second period;

a seventh switch, one terminal of which is connected to the connection point of said sixth switch and said third capacitor, said switch being turned OFF in said first period and turned ON in said second period, and at least the potential at the other terminal of said third capacitor being input to said amplifier;

an eighth switch, one terminal of which receives said DC bias voltage and the other terminal of which is connected to the connection point of said third capacitor and said fourth capacitor, and said switch being turned ON in said first period and turned OFF in said second period;

a ninth switch, one terminal of which receives said analog input signal or said DC bias voltage and the other terminal of which is connected to one terminal of said fourth capacitor, not connected to said third capacitor, said switch being turned ON in said first period and turned OFF in said second period; and

a tenth switch, one terminal of which is connected to the connection point of said fourth capacitor and said ninth switch and the other terminal of which is connected to the output terminal of said amplifier, and said switch being turned OFF in said first period and turned ON in said second period.

3. The pipeline A/D converter in accordance with claim 1 , wherein the conductance of an output stage of said amplifier is switched according to said mode.

4. The pipeline A/D converter in accordance with claim 1 , wherein said mode is fixed using electrical wiring.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2014
From: PANASONIC CORPORATION
To: COLLABO INNOVATIONS, INC.
Reel/Frame 033021/0806 →
LIEN Recorded Jan 13, 2014
From: COLLABO INNOVATIONS, INC.
To: PANASONIC CORPORATION
Reel/Frame 031997/0445 →
CHANGE OF NAME Recorded Jan 8, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 031947/0358 →