Semiconductor integrated circuit
View Patent ↗The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.
1. A semiconductor integrated circuit comprising:
a data non-holding circuit corresponding to a logic circuit which unholds data therein in a standby mode;
a data holding circuit corresponding to a logic circuit which needs to hold data therein in the standby mode;
a virtual high potential source line connected to source electrodes of respective p-type field effect transistors provided within the data non-holding circuit;
a first high potential source line connected to source electrodes of respective p-type field effect transistors provided within the data holding circuit;
a second high potential source line supplied with a potential higher than a potential of the first high potential source line;
a first high potential switch which connects the first high potential source line and the virtual high potential source line in an operation mode and allows the virtual high potential source line to float in the standby mode;
a second high potential switch which connects substrate terminals of the respective p-type field effect transistors provided within the data holding circuit and the first high potential source line in the operation mode and connects the substrate terminals and the second high potential source line in the standby mode; and
a gate circuit which inputs an output signal of the data non-holding circuit to the data holding circuit in the operation mode and fixes an input signal value of the data holding circuit in the standby mode.
2. The semiconductor integrated circuit according to claim 1 , further comprising:
a virtual low potential source line connected to source electrodes of respective n-type field effect transistors provided within the data non-holding circuit;
a first low potential source line connected to source electrodes of respective n-type field effect transistors provided within the data holding circuit;
a second low potential source line supplied with a potential lower than a potential of the first low potential source line;
a first low potential switch which connects the first low potential source line and the virtual low potential source line in the operation mode and allows the virtual low potential source line to float in the standby mode; and
a second low potential switch which connects substrate terminals of the respective n-type field effect transistors provided within the data holding circuit in the operation mode and connects the substrate terminals and the second low potential source line in the standby mode.
3. The semiconductor integrated circuit according to claim 1 , further comprising a low potential source line connected to the source electrodes and substrate terminals of the respective n-type field effect transistors respectively provided within the data non-holding circuit and the data holding circuit.
4. The semiconductor integrated circuit according to any of claims 1 , further comprising a voltage regulator including a differential amplifier which outputs a potential corresponding to a difference between the potential of the first high potential source line and a reference potential, and a voltage supply field effect transistor which has one end connected to the first high potential source line, the other end connected to the second high potential source line and a control terminal inputted with the potential outputted from the differential amplifier.
5. The semiconductor integrated circuit according to claim 3 , wherein each of the substrate terminals of the respective field effect transistors provided within the data non-holding circuit is connected to an external terminal which inputs a substrate control potential from outside.