Array substrate for a liquid crystal display device having multi-layered metal line and fabricating method thereof

1. An array substrate for a liquid crystal display device, comprising:

a substrate;

a gate electrode and a gate line on the substrate;

a gate insulating layer on the gate electrode and the gate line;

an active layer on the gate insulating layer;

an ohmic contact layer on the active layer;

source and drain electrodes and a data line on the ohmic contact layer, the source and drain electrodes and the data line having multiple metal layers;

a passivation layer on the source and drain electrodes and the data line; and

a pixel electrode on the passivation layer,

wherein an oxide film is formed between first and second metal layers of the multiple metal layers, and wherein the first and second metal layers do not contact each other with the oxide film therebetween.

2. The substrate according to claim 1 , wherein the oxide film is a metal oxide film.

3. The substrate according to claim 2 , wherein the metal oxide film has a thickness less than about 50 Å.

4. An array substrate for a liquid crystal display device, comprising:

a substrate;

a gate electrode and a gate line on the substrate;

a gate insulating layer on the gate electrode and the gate line;

an active layer on the gate insulating layer;

an ohmic contact layer on the active layer;

source and drain electrodes and a data line on the ohmic contact layer, the source and drain electrodes and the data line having multiple metal layers including a first metal layer of chromium (Cr), a second metal layer of aluminum (Al), and a third metal layer of molybdenum (Mo), wherein the third metal layer has a thickness less than about 100 Å;

a passivation layer on the source and drain electrodes and the data line; and

a pixel electrode on the passivation layer.

5. The substrate according to claim 4 , further comprising a gate pad connected to the gate line.

6. The substrate according to claim 4 , further comprising a data pad connected to the data line.

7. The substrate according to claim 4 , further comprising a source-drain metal layer on the gate insulating layer over a portion of the gate line.

8. The substrate according to claim 7 , wherein the source-drain metal layer is connected to the pixel electrode through a contact hole through the passivation layer.

9. The substrate according to claim 4 , wherein the source and drain electrodes and the data line further includes a third metal layer of molybdendum (Mo) on the second metal layer.