Semiconductor integrated circuit device and substrate bias controlling method

1. A semiconductor integrated circuit device comprising:

a first bias generating circuit configured to generate a first substrate bias voltage of a P-channel transistor;

a second bias generating circuit configured to generate a second substrate bias voltage of a N-channel transistor; and

a control circuit configured to control said first bias generating circuit and said second bias generating circuit independently on the basis of operating states of circuits to which said first substrate bias voltage and said second substrate bias voltage are applied,

wherein said control circuit operates in synchronization with a clock signal, and controls only one of said first substrate bias voltage and said second substrate bias voltage in one period of said clock signal.

2. A semiconductor integrated circuit device comprising:

a first bias generating circuit configured to generate a first substrate bias voltage of a P-channel transistor;

a second bias generating circuit configured to generate a second substrate bias voltage of a N-channel transistor;

a control circuit configured to control said first bias generating circuit and said second bias generating circuit independently on the basis of operating states of circuits to which said first substrate bias voltage and said second substrate bias voltage are applied;

a delay monitor portion configured to measure a delay time of a first circuit included in said circuits to which said first substrate bias voltage and said second substrate bias voltage are applied and output a comparison result between said delay time of the first circuit and a predetermined delay time; and

a PN balance monitor portion configured to measure a balance between an on-current of said P-channel transistor and on-current of said N-channel transistor and output a PN balance signal,

wherein said control circuit controls said first bias generating circuit and said second bias generating circuit independently on the basis of said comparison result and said PN balance signal.

3. The semiconductor integrated circuit device according to claim 2 , wherein said PN balance monitor portion includes:

a first delay circuit configured to generate a delay time which depends on a characteristic of said P-channel transistor,

a second delay circuit configured to generate a delay time which depends on a characteristic of said N-channel transistor, and

a first PN balance signal generating circuit configured to generate said PN balance signal on the basis of a difference between said delay time generated by said first delay circuit and said delay time generated by said second delay circuit.

4. The semiconductor integrated circuit device according to claim 3 , wherein said PN balance monitor portion includes:

a second PN balance signal generating circuit configured to generate a second PN balance signal indicating whether or not said difference is in a predetermined range and output said second PN balance signal to said control circuit,

wherein said control circuit controls said first bias generating circuit and said second bias generating circuit independently such that a delay time is most close to said predetermined delay time in said predetermined range on the basis of said second PN balance signal.

5. The semiconductor integrated circuit device according to claim 3 , wherein said first delay circuit includes:

a plurality of AND circuits configured to be cascade-connected to each other, and

wherein said second delay circuit includes:

a plurality of OR circuits configured to be cascade-connected to each other.

6. The semiconductor integrated circuit device according to claim 3 , wherein said first delay circuit includes:

a plurality of NAND circuits configured to be cascade-connected to each other, and

wherein said second delay circuit includes:

a plurality of NOR circuits configured to be cascade-connected to each other.

7. The semiconductor integrated circuit device according to claim 2 , wherein said delay monitor portion includes:

a clock delay circuit configured to output a first delay clock signal to which a clock signal is delayed by said first circuit,

a comparison portion configured to output a comparison result between said clock signal and said first delay clock signal,

wherein said PN balance monitor portion includes:

a first delay circuit configured to output a second delay clock signal to which said clock signal is delayed by said P-channel transistor,

a second delay circuit configured to output a third delay clock signal to which said clock signal is delayed by said N-channel transistor,

a PN balance signal generating circuit configured to output said PN balance signal on the basis of said second delay clock signal and said third delay clock signal.

8. The semiconductor integrated circuit device according to claim 7 , wherein said first delay circuit outputs a fourth delay clock signal whose delay time is short by a time which corresponds to a predetermined number of said P-channel transistor,

said second delay circuit outputs a fifth delay clock signal whose delay time is short by a time which corresponds to a predetermined number of said N-channel transistor,

wherein said PN balance monitor portion further includes:

a second PN balance signal generating circuit configured to output a second PN balance signal indicating whether or not a delay difference between said fourth delay clock signal and said third delay clock signal is in a predetermined range, and

a third PN balance signal generating circuit configured to output a third PN balance signal indicating whether or not a delay difference between said fifth delay clock signal and said second delay clock signal is in a predetermined range,

wherein said control circuit controls said first bias generating circuit and said second bias generating circuit independently such that a delay time is most close to said predetermined delay time in said predetermined range on the basis of said second PN balance signal and said third PN balance signal.

9. The semiconductor integrated circuit device according to claim 8 , wherein said first delay circuit includes:

a plurality of AND circuits configured to be cascade-connected to each other, and

wherein said second delay circuit includes:

a plurality of OR circuits configured to be cascade-connected to each other.

10. A substrate bias controlling method comprising:

(a) generating a first substrate bias voltage of a P-channel transistor;

(b) generating a second substrate bias voltage of a N-channel transistor; and

(c) controlling said first bias generating circuit and said second bias generating circuit independently on the basis of operating states of circuits to which said first substrate bias voltage and said second substrate bias voltage are applied,

wherein said step (c) includes:

(c1) controlling only one of said first substrate bias voltage and said second substrate bias voltage in one time.

11. A substrate bias controlling method comprising:

(a) generating a first substrate bias voltage of a P-channel transistor;

(b) generating a second substrate bias voltage of a N-channel transistor;

(c) controlling said first bias generating circuit and said second bias generating circuit independently on the basis of operating states of circuits to which said first substrate bias voltage and said second substrate bias voltage are applied;

(d) measuring a delay time of a first circuit included in said circuits to which said first substrate bias voltage and said second substrate bias voltage are applied and outputting a comparison result between said delay time of the first circuit and a predetermined delay time; and

(e) measuring a balance between an on-current of said P-channel transistor and on-current of said N-channel transistor and outputting a PN balance signal,

wherein said step (c) includes:

(c2) controlling said first bias generating circuit and said second bias generating circuit independently on the basis of said comparison result and said PN balance signal.

12. The substrate bias controlling method according to claim 11 , wherein said step (e) includes:

(e1) generating said PN balance signal on the basis of a difference between a delay time depending on a characteristic of said P-channel transistor and a delay time depending on a characteristic of said N-channel transistor.

13. The substrate bias controlling method according to claim 12 , wherein said step (e) includes:

(e2) generating a second PN balance signal indicating whether or not said difference is in a predetermined range and outputting said second PN balance signal to said control circuit,

wherein said step (c) includes:

(c3) controlling said first bias generating circuit and said second bias generating circuit independently such that a delay time is most close to said predetermined delay time in said predetermined range on the basis of said second PN balance signal.