Semiconductor memory device

1 . A semiconductor memory device including an SRAM, wherein a gate electrode of a MOS transistor connected with a word line and a bit line in the SRAM has a projection extending in a direction away from a contact electrically connecting a drain region of the MOS transistor and the bit line, and

a contact electrically connecting the gate electrode and the word line is provided in the projection.

2 . The semiconductor memory device of claim 1 , comprising a DRAM,

wherein the bit line in the SRAM and a bit line in the DRAM are formed in a common interconnect layer.

3 . The semiconductor memory device of claim 2 , wherein the DRAM has a stacked capacitor, and

the layer where the bit lines are formed is above the capacitor.

4 . A semiconductor memory device including an SRAM, the device comprising:

a conductive projection, which is in contact with a gate electrode of a MOS transistor connected with a word line and a bit line in the SRAM and extends in a direction away from a contact electrically connecting a drain region of the MOS transistor and the bit line, and

a contact electrically connecting the projection and the word line.

5 . The semiconductor memory device of claim 4 , comprising a DRAM,

wherein the bit line in the SRAM and a bit line in the DRAM are formed in a common interconnect layer.

6 . The semiconductor memory device of claim 5 , wherein the DRAM has a stacked capacitor, and

the layer where the bit lines are formed is above the capacitor.

7 . A semiconductor memory device including an SRAM, wherein a first MOS transistor and a second MOS transistor are connected to a common word line in the SRAM and have a common gate electrode, and a contact that electrically connects the gate electrode and the word line is provided outside a region surrounded by contacts that are connected with a drain region and a source region respectively of the first MOS transistor and by contacts that are connected with a drain region and a source region respectively of the second MOS transistor.

8 . The semiconductor memory device of claim 7 , comprising a DRAM,

wherein a bit line in the SRAM and a bit line in the DRAM are formed in a common interconnect layer.

9 . The semiconductor memory device of claim 8 , wherein the DRAM has a stacked capacitor, and

the layer where the bit lines are formed is above the capacitor.

10 . The semiconductor memory device of claim 7 , wherein a bit line and an inverted bit line in the SRAM are twisted together, the inverted bit line being obtained by inverting logic of the bit line.