Memory system comprising a controller managing independent data transfer between input-output terminal, synchronous dynamic random access memory, and flash memory
View Patent ↗A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
1. A flash memory system comprising:
a controller;
a Synchronous Dynamic Random Access memory having a clock terminal, an address strobe terminal, an enable terminal, an address terminal, and a data input/output terminal;
a flash memory;
an input-output terminal;
a first signal line coupled between said input/output terminal and said controller;
second signal lines coupled between said controller and said Synchronous Dynamic Random Access memory; and
a third signal line coupled between said controller and said flash memory,
wherein said second signal lines include a clock signal line for supplying a clock signal to said clock terminal of said Synchronous Dynamic Random Access memory and a data line for data transfer between said controller and said data input/output terminal of said Synchronous Dynamic Random Access memory,
wherein said controller controls to carry out a data transfer between said Synchronous Dynamic Random Access memory and said controller itself via said data line in response to said clock signal when an enable signal is supplied to said enable terminal of said Synchronous Dynamic Random Access memory, after a first address is supplied to said address terminal of said Synchronous Dynamic Random Access memory accompanied with an enable signal to said address strobe terminal of said Synchronous Dynamic Random Access memory,
wherein said controller controls to carry out a first data transfer between said input/output terminal and said Synchronous Dynamic Random Access memory via both of said first signal line and said data line, and to carry out a second data transfer between said Synchronous Dynamic Random Access memory and said flash memory via both of said data line and said third signal line, and
wherein said controller is adapted to carry out said first data transfer and said second data transfer at least partially concurrently.
2. A flash memory system according to claim 1 ,
wherein said first data transfer comprises a plurality of first unit data transfers as said first data transfer,
wherein said second data transfer comprises a plurality of second unit data transfers as said second data transfer, and
wherein said controller is adapted to carry out a first unit data transfer and a second unit data transfer at least partially non-concurrently.
3. A flash memory system according to claim 2 ,
wherein said controller is adapted to carry out an arbitrary one of said first unit data transfer and said second unit data transfer in response to an edge of said clock signal.
4. A flash memory system according to claim 1 ,
wherein said first data transfer comprises a plurality of first unit data transfers as said first data transfer,
wherein said second data transfer comprises a plurality of second unit data transfers as said second data transfer, and
wherein said controller is adapted to carry out said plurality of first unit data transfers and said plurality of second unit data transfers as a time sharing operation.
5. A flash memory system according to claim 4 ,
wherein a data transfer rate of said first data transfer is higher than a data transfer rate of said second data transfer.
6. A flash memory apparatus comprising:
a controller;
a Synchronous Dynamic Random Access memory having a clock terminal, an address strobe terminal, an enable terminal, an address terminal, and a data input/output terminal, and being adapted to input data in response to a clock signal to said clock terminal, and being adapted to output data in response to a clock signal to said clock terminal,
a flash memory which includes a plurality of memory cells, each of which is capable of electrically erasing data and of electrically programming data; and
an input/output terminal;
a first signal line coupled between said input/output terminal and said controller;
a second signal line coupled between said controller and said Synchronous Dynamic Random Access memory; and
a third signal line coupled between said controller and said flash memory,
wherein said controller is adapted to carry out a data transfer via said second signal line in response to a clock signal when an enable signal is supplied to said enable terminal of said Synchronous Dynamic Random Access memory, after a first address is supplied to said address terminal of said Synchronous Dynamic Random Access memory accompanied with an enable signal to said address strobe terminal of said Synchronous Dynamic Random Access memory,
wherein said controller controls to carry out a first data transfer between said input/output terminal and said Synchronous Dynamic Random Access memory via both of said first signal line and said second signal line, and to carry out a second data transfer between said Synchronous Dynamic Random Access memory and said flash memory via both of said second signal line and said third signal line, and
wherein said controller is adapted to carry out a first period of said first data transfer and a second period of said second data transfer in parallel.
7. A flash memory apparatus according to claim 6 ,
wherein said first period of said first data transfer comprises a plurality of first unit data transfers as said first data transfer,
wherein said second period of said second data transfer comprises a plurality of second unit data transfers as said second data transfer, and
wherein said controller is adapted to carry out a first unit data transfer and a second unit data transfer not in parallel.
8. A flash memory apparatus according to claim 7 ,
wherein said controller is adapted to carry out an arbitrary one of said first unit data transfer and said second unit data transfer in response to an edge of a clock signal.
9. A flash memory apparatus according to claim 6 ,
wherein said first period of said first data transfer comprises a plurality of first unit data transfers as said first data transfer,
wherein said second period of said second data transfer comprises a plurality of second unit data transfers as said second data transfer, and
wherein said controller is adapted to carry out said plurality of first unit data transfers and said plurality of second unit data transfers as a time sharing operation.
10. A flash memory apparatus according to claim 9 ,
wherein said controller is adapted to carry out another period of said first data transfer and another period of said second data transfer without being in parallel.