Non-volatile semiconductor storage device
View Patent ↗In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.
1. A non-volatile semiconductor storage device comprising:
a non-volatile storage section at which a pair of memory cells to which data with mutually opposite values are written is plurally provided; and
a detector which, when a selection signal is respectively inputted to the memory cell pair that is a data-reading object, detects the data that have been written to the data-reading object memory cell pair on the basis of a magnitude relationship of voltages of a first signal line and a second signal line, which are connected to different memory cells of the data-reading object memory cell pair, after a voltage of one of the first and second signal lines has changed across a threshold due to currents corresponding to the data written to the data-reading object memory cell pair respectively flowing in the data-reading object memory cell pair.
2. The non-volatile semiconductor storage device of claim 1 , further comprising a charging section which charges the first signal line and the second signal line,
wherein the detector respectively inputs the selection signal to the data reading object memory cell pair after the first and second signal lines have been charged by the charging section.
3. The non-volatile semiconductor storage device of claim 1 , wherein the detector comprises a detection circuit which
(a) while neither of the voltages of the first and second signal lines has changed across the threshold, outputs a first output signal and a second output signal which are signals at the same level, and
(b) when the voltage of one of the first and second signal lines changes across the threshold, causes the levels of the first and second output signals to differ, and switches a magnitude relationship of the levels of the first and second output signals in accordance with whether the signal line whose voltage has changed across the threshold is the first signal line or the second signal line,
and the detector outputs one of the first and second output signals as reading data.
4. The non-volatile semiconductor storage device of claim 1 , further comprising an operation-stopping controller which, with the change of the voltage of one of the first and second signal lines across the threshold as a trigger, stops operations of peripheral circuits, including the charging section and the detector.
5. The non-volatile semiconductor storage device of claim 1 , further comprising a latching section which, with the change of the voltage of one of the first and second signal lines across the threshold as a trigger, latches reading data outputted from the detector.
6. The non-volatile semiconductor storage device of claim 2 , wherein the non-volatile storage section comprises a plurality of bit lines, each memory cell provided at the non-volatile storage section being connected to one of the plurality of bit lines such that the two memory cells that structure one of the memory cell pairs are connected to mutually different bit lines, and
of the plurality of bit lines, the charging section charges, via the first signal line and the second signal line, only the two bit lines that are connected to the data reading object memory cell pair, and when detection by the detector of the data written to the data reading object memory cell pair has finished, the charging section discharges the two bit lines to a reference voltage.
7. The non-volatile semiconductor storage device of claim 6 wherein, at the non-volatile storage section in which the cell pairs are plurally provided, the plurality of cell pairs and the plurality of bit lines are arranged such that, between the two bit lines that are connected to the two memory cells structuring one of the memory cell pairs, bit lines that are connected to the memory cells of other memory cell pairs are disposed.