Semiconductor device with signal line having decreased characteristic impedance
View Patent ↗A semiconductor device includes a semiconductor chip, electrodes pads, first and second insulating layers, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The first insulating layer is formed on the first and second areas of the semiconductor chip and exposes the electrode pads. The first conductive pattern transfers a signal and is formed on the first insulating layer. A second insulating layer is formed on the first conductive pattern and the first insulating layer. The second conductive pattern is formed on the second insulating layer and provides a ground potential. The external terminals are formed on the first and second patterns at the second area.
1. A semiconductor device, comprising:
a semiconductor chip having a main surface, wherein the main surface has a first area, and a second area located outside and adjacently to the first area;
first, second and third electrode pads formed on the main surface in the second area, wherein the first, second and third electrode pads are aligned with each other and wherein the second electrode pad is located between the first and third electrode pads;
a first insulating layer formed on the main surface in the first and second areas, wherein the first, second and third electrode pads are exposed from the first insulating layer;
a first exterior terminal formed above a top surface of the first insulating layer in the first area;
a second exterior terminal formed above the top surface of the first insulating layer in the first area;
a first conductive pattern extending on the top surface of the first insulating layer, the first conductive pattern electrically connected to the second electrode pad, and electrically connected to the second exterior terminal;
a second insulating layer formed on the first insulating layer and on the first conductive pattern; and
a second conductive pattern extending on a top surface of the second insulating layer, the second conductive pattern electrically connected to the first and third electrode pads and the first exterior terminal,
wherein the second conductive pattern is positioned along lateral sides of the second exterior terminal to entirely surround the second exterior terminal.
2. The semiconductor device according to claim 1 , wherein the first exterior terminal has a ground potential applied thereto.
3. The semiconductor device according to claim 1 , wherein at least the second conductive pattern and the second insulating layer are covered by a dielectric layer.
4. The semiconductor device according to claim 1 , wherein the second conductive pattern has an opening to expose the second exterior terminal.
5. The semiconductor device according to claim 1 , wherein the second insulating layer is a polymide membrane.
6. The semiconductor device according to claim 1 , wherein the second insulating layer is a phenol resin.
7. A semiconductor device, comprising:
a semiconductor chip having a main surface, wherein the main surface has a first area, and a second area located outside and adjacently to the first area;
first, second and third electrode pads formed on the main surface in the second area, wherein the first, second and third electrode pads are aligned with each other and wherein the second electrode pad is located between the first and third electrode pads;
a first insulating layer formed on the main surface in the first and second areas, wherein the first, second and third electrode pads are exposed from the first insulating layer;
a first exterior terminal formed above a top surface of the first insulating layer in the first area;
a second exterior terminal formed above the top surface of the first insulating layer in the first area;
a first conductive pattern extending on the top surface of the first insulating layer, the first conductive pattern electrically connected to the second electrode pad, and electrically connected to the second exterior terminal;
a second insulating layer formed on the first insulating layer and on the first conductive pattern; and
a second conductive pattern extending on a top surface of the second insulating layer, the second conductive pattern electrically connected to the first and third electrode pads and the first exterior terminal,
wherein a width of the second conductive pattern is wider than a width of the first conductive pattern, and wherein the second conductive pattern is positioned along lateral sides of the second exterior terminal to entirely surround the second exterior terminal.
8. The semiconductor device according to claim 7 , wherein the first exterior terminal has a ground potential applied thereto.
9. The semiconductor device according to claim 7 , wherein at least the second conductive pattern and the second insulating layer are covered by a dielectric layer.
10. The semiconductor device according to claim 7 , wherein the second conductive pattern has an opening to expose the second exterior terminal.
11. The semiconductor device according to claim 7 , wherein the second insulating layer is a polymide membrane.
12. The semiconductor device according to claim 7 , wherein the second insulating layer is a phenol resin.