Granted Patent B2

US 8,127,199 · App. 11/787,228 · Granted Feb 28, 2012

Abstract

Claims (60)

1. A method of interleaving data comprising:

receiving a plurality of symbols from two data paths, each data path associated with a different type of data;

sorting the symbols to group them according to the type of data they represent;

packing the sorted symbols in a first memory of an interleaver to accumulate full burst blocks of data that can be accommodated by a second memory of said interleaver, with each full burst block containing only one of the data types; and

burst writing the accumulated full burst blocks of data to said second memory.

2. The method of claim 1 , wherein:

said first memory comprises SRAM and said second memory comprises SDRAM, the size of said SRAM being substantially smaller than the size of said SDRAM.

3. The method of claim 2 , wherein:

after sorting, there is only one break in a sequential write address for each full block to be written into said second memory of said interleaver.

4. The method of claim 1 , wherein:

after sorting, there is only one break in a sequential write address for each full block to be written into said second memory of said interleaver.

5. The method of claim 1 , further comprising:

providing a plurality of symbol channels.

6. A method of interleaving data comprising:

providing two interleaver data paths, each path associated with a different type of data;

packing symbols from said data paths in a first memory of an interleaver to accumulate sorted blocks of data having a full burst length that can be accommodated by a second memory of said interleaver, with each block only containing data from a respective one of the data paths; and

burst writing the accumulated full blocks of data to said second memory, each full block being written to the second memory in a sequential burst.

7. The method of claim 6 , wherein:

said second memory is SDRAM;

the symbols are 8 bit FEC symbols;

said packing step accumulates data for four FEC symbols at a time; and

data is written 32 bits at a time to said SDRAM.

8. The method of claim 6 , wherein:

prior to packing, the symbols are sorted to minimize a number of write address breaks required to write data into said second memory.

9. A method of interleaving data comprising:

storing dual path Interleaver data in an interleaver SDRAM, wherein each of said dual paths is associated with a different type of data, by:

first writing the data in a staggered pattern in SRAM of said interleaver such that a linear read can be done from said SRAM, said staggered pattern alternating between data from one of said dual paths and data from the other of said dual paths; and

subsequently writing blocks of the data from said SRAM to said SDRAM in bursts, wherein said blocks are organized to minimize the number of write accesses required by said bursts.

10. The method of claim 9 , further comprising:

restarting the staggering within a commutator loop to keep the SRAM small while maintaining the structure of said interleaver and the burst write feature to the SDRAM.

11. The method of claim 9 , wherein:

the data is stored in the SDRAM such that a linear 32 bit read will provide he a data stream that represents the stream from said interleaver.

12. A method of interleaving data comprising:

providing a plurality of symbols on two data paths, each data path associated with a different type of data;

sorting the symbols to group them according to the type of data they represent;

packing the sorted symbols in SRAM of an interleaver as burst blocks adapted to minimize the number of write accesses required to subsequently write the burst blocks into SDRAM; and

burst writing the burst blocks from said SRAM to said SDRAM;

wherein, after said sorting step, there is only one break in a write address for writing the burst blocks into SDRAM;

further comprising:

before writing to SDRAM, accumulating data for four FEC symbols at a time; and

writing four symbols wide to optimize SDRAM access time;

wherein:

the FEC symbols are 8 bits;

data is written 32 bits at a time to SDRAM to fit the SDRAM interface, and

data is written to SDRAM in a staggered pattern from said SRAM such that a linear read can be done to gain speed.

13. The method of claim 12 , further comprising:

restarting the staggered pattern within a commutator loop to keep the SRAM small while maintaining the structure of said interleaver and the burst write feature to the SDRAM.

14. A method of interleaving data comprising:

receiving a plurality of symbols, wherein each of the symbols is assigned to one of two paths each associated with a different type of data; and

sorting the symbols so that all of the symbols assigned to one of the two paths are grouped together, and all of the symbols assigned to another of the two paths are grouped together; and

using SRAM, packing the sorted symbols in a staggered pattern of burst blocks so that data can be burst written to SDRAM;

wherein said burst blocks are of a size adapted to optimize the efficient writing of data to said SDRAM.

15. The method of claim 14 , further comprising:

when the SRAM has a full block corresponding to a SDRAM burst block, performing a full length burst write from SRAM to SDRAM.

16. Apparatus for interleaving data comprising:

means for sorting symbols which are assigned to one of two paths, each path associated with a different type of data, and grouping the symbols so that symbols which are assigned to one of the two paths are grouped together and symbols which are assigned to the other of the two paths are grouped together;

means for storing the sorted symbols in a staggered pattern so that data can be subsequently burst written to SDRAM; and

means for burst writing the symbols to SDRAM.

17. The apparatus of claim 16 , wherein:

the means for storing the sorted symbols in a staggered pattern comprises SRAM.

Assignments (8)