Antimonide-based compound semiconductor with titanium tungsten stack

1. An apparatus, comprising:

an antimonide-based compound semiconductor (ABCS) stack;

an upper barrier layer of indium, aluminum, and arsenic formed on the ABCS stack;

a gate stack formed on the upper barrier layer;

wherein the gate stack comprises a base layer that consists of titanium and tungsten, the base layer being formed on the upper barrier layer, the base layer having a thickness of approximately 20-50 angstroms,

wherein a gate barrier layer is formed on the base layer; and

wherein the gate barrier layer comprises a lower gate barrier layer comprising titanium, and an upper gate barrier layer comprising platinum.

2. The apparatus of claim 1 , further comprising a contact layer formed on the gate barrier layer.

3. The apparatus of claim 2 , wherein the upper gate barrier layer is formed on the lower gate barrier layer; and

wherein the contact layer comprises a layer of gold.

4. The apparatus of claim 3 , wherein the lower gate barrier layer, the upper gate barrier layer, and the contact layer of the gate stack comprise approximate thicknesses between 300-400 angstroms, 300-500 angstroms, and 4500-6500 angstroms, respectively;

wherein the upper barrier layer comprises a thickness of approximately 40 angstroms.

5. The apparatus of claim 1 , wherein the ABCS stack comprises:

a semi-insulating substrate;

a first buffer layer formed on the semi-insulating substrate;

a second buffer layer formed on the first buffer layer;

a first electron barrier formed on the second buffer layer;

a channel layer formed on the first electron barrier;

a second electron barrier layer formed on the channel layer;

an n-type layer formed on the second electron barrier; and

a third electron barrier layer formed on the n-type layer;

wherein the upper barrier layer is formed on the third electron barrier layer.

6. The apparatus of claim 5 , wherein at least one of the first electron barrier layer, the second electron barrier layer, and the third electron barrier layer comprise antimony.

7. The apparatus of claim 5 , wherein the first electron barrier layer, the second electron barrier layer, and the third electron barrier layer comprise aluminum and antimony.

8. The apparatus of claim 7 , wherein the first electron barrier layer, the second electron barrier layer, and the third electron barrier layer comprise approximate thicknesses of 500, 75, and 12 angstroms, respectively.

9. The apparatus of claim 7 , wherein the semi-insulating substrate comprises gallium arsenide;

wherein the first buffer layer comprises gallium arsenide;

wherein the second buffer layer comprises aluminum gallium antimonide;

wherein the channel layer comprises indium arsenide;

wherein the n-type layer comprises indium arsenide and silicon.

10. The apparatus of claim 9 , wherein the second buffer layer comprises Al 0.7 Ga 0.3 Sb.

11. The apparatus of claim 10 , wherein the first buffer layer, the second buffer layer, the channel layer, and the n-type layer comprise approximate thicknesses of 0.25 microns, 2 microns, 150 angstroms, and 12 angstroms, respectively.

12. A high electron mobility transistor, comprising:

an antimonide-based compound semiconductor (ABCS) stack;

an upper barrier layer formed on the ABCS stack;

a gate stack formed on the upper barrier layer;

wherein the gate stack comprises a first diffusion prevention layer comprising a base layer that consists of titanium and tungsten, the base layer being formed on the upper barrier layer, a gate barrier layer formed on the base layer, and a contact layer formed on the gate barrier layer;

wherein the base layer is configured to provide a thermally stable contact with the upper barrier layer, the base layer having a thickness of approximately 20-50 angstroms,

wherein the gate barrier layer is configured to prevent the contact layer from diffusing into the ABCS stack; and

wherein the gate barrier layer further comprises a second diffusion prevention layer formed on the base layer and a third diffusion prevention layer formed on the second diffusion prevention layer where the second diffusion prevention layer comprises a lower gate barrier layer comprising titanium, and the third diffusion prevention layer comprises an upper gate barrier layer comprising platinum.

13. The high electron mobility transistor of claim 12 , wherein the upper barrier layer comprises indium, aluminum, and arsenic;

wherein the contact layer comprises a gold layer.

14. The high electron mobility transistor of claim 13 , further comprising:

an indium arsenide cap layer formed on the upper barrier layer;

a source contact and a drain contact formed on the indium arsenide cap layer adjacent to the gate stack;

wherein the ABCS stack comprises the following layers:

a gallium arsenide substrate, a gallium arsenide buffer layer, an aluminum gallium antimony buffer layer, a first aluminum antimonide layer, an indium arsenide layer, a second aluminum antimonide layer, an indium arsenide and silicon layer, and a third aluminum antimonide layer;

wherein the upper barrier layer is formed on the third aluminum antimonide layer; and

wherein the lower gate barrier layer is approximately 300-400 angstroms thick and the upper gate barrier layer is approximately 300-500 angstroms thick.