Array substrate capable of improving display quality
View Patent ↗The charging voltage of a pixel electrode varies when there is a photo-misalignment of the pixel electrode, and such variation degrades the display quality. An array substrate that prevents fluctuation in the charging voltage of a pixel electrode is presented. The array substrate includes a pixel electrode, a gate wiring formed on the pixel electrode, and a data wiring that includes a first data line and a second data line formed two sides of the pixel electrode. A first voltage-maintaining electrode is separated from a first side of the first data line by a first distance, and a second voltage-maintaining electrode is separated from a second side of the first data line by a second distance. Both voltage-maintaining electrodes are electrically connected to the pixel electrode. A thin-film transistor is electrically connected to the gate wiring, the data wiring and the pixel electrode.
1. An array substrate comprising:
a pixel electrode that contains a transparent conductive material;
a gate wiring formed on an upper or lower portion of the pixel electrode and extending in a first direction;
a data wiring including a first data line formed on a left side of the pixel electrode and extending in a second direction that is nonparallel to the first direction, and a second data line that is formed on a right side of the pixel electrode and extending in the second direction;
a first voltage-maintaining electrode spaced by a first distance from the first data line along the first direction, the first voltage-maintaining electrode being electrically connected to the pixel electrode;
a second voltage-maintaining electrode spaced by a second distance from the second data line along the first direction, the second voltage-maintaining electrode being electrically connected to the pixel electrode;
a thin-film transistor electrically connected to the gate wiring, the data wiring and the pixel electrode, and
a storage wiring extending in the second direction across the pixel electrode, the storage wiring and the data wiring being formed from the same layer,
wherein the pixel electrode is separated from the first data line by a third distance along the first direction, and the third distance is greater than or equal to the first distance.
2. The array substrate of claim 1 , wherein the pixel electrode is longer in the first direction than in the second direction.
3. The array substrate of claim 1 , wherein the first and second voltage-maintaining electrodes are formed from the same layer as the data wiring.
4. The array substrate of claim 3 , wherein the first distance is substantially equal to the second distance.
5. The array substrate of claim 4 , wherein a range of the first distance is about 5 μm to 7 μm.
6. The array substrate of claim 4 , wherein
the pixel electrode is separated from the second data line by a fourth distance, and
the third distance is substantially equal to the fourth distance.
7. The array substrate of claim 3 , further comprising a protection layer that is disposed between the first and second voltage-maintaining electrodes and the pixel electrode,
a first contact hole and a second contact hole are formed in the protection layer, the first contact hole being electrically connected to the first voltage-maintaining electrode and the pixel electrode, and the second contact hole being electrically connected to the second voltage-maintaining electrode and the pixel electrode.
8. The array substrate of claim 7 , wherein the first voltage-maintaining electrode and the second voltage-maintaining electrode are arranged symmetrically with respect to an imaginary line that is disposed at a center portion of the pixel electrode and extends in the second direction.
9. The array substrate of claim 8 , wherein the first voltage-maintaining electrode comprises a first contact part that is electrically connected to the pixel electrode through the first contact hole and a first extending part extending from the first contact part in the second direction, and
the second voltage-maintaining electrode comprises a second contact part that is electrically connected to the pixel electrode through the second contact hole and a second extending part extending from the second contact part in the second direction.
10. The array substrate of claim 9 , wherein each of the first and second extending parts has a width of about 6 μm to about 8 μm measured along the first direction.
11. The array substrate of claim 9 , wherein the drain electrode of the thin-film transistor is directly connected to one of the first contact part and the second contact part.
12. The array substrate of claim 11 , wherein the pixel electrode is formed to define a pixel area, and wherein the pixel electrode is one of multiple pixel electrodes defining multiple pixel areas disposed in a matrix configuration having rows, even-numbered columns, and odd-numbered columns, and the first and second voltage-maintaining electrodes and the thin-film transistor are disposed in the pixel areas defined by the pixel electrodes,
each of drain electrodes of the thin-film transistors disposed in one of the even numbered columns is electrically connected to the first contact part of the first voltage-maintaining electrode that are disposed in the same column, and each of drain electrodes of the thin-film transistors disposed in one of the odd-numbered columns is electrically connected to the second contact part of the second voltage-maintaining electrode that are disposed in the same column.
13. The array substrate of claim 12 , wherein each of the drain electrode of the thin-film transistors disposed along the even-numbered column and the drain electrode of the thin-film transistors disposed along the odd-numbered column is formed on an imaginary line extending in the second direction.
14. The array substrate of claim 13 , wherein each of the drain electrode of the thin-film transistors disposed along the even-numbered column and the drain electrode of the thin-film transistors disposed along the odd-numbered column is formed on an imaginary line substantially parallel to the length of the data wiring.
15. A display panel comprising:
a first substrate;
a second substrate having a common electrode substantially parallel to the first substrate; and
a liquid crystal layer disposed between the first substrate and the second substrate, wherein the first substrate comprises:
a pixel electrode that contains a transparent conductive material;
a gate wiring formed on an upper or lower portion of the pixel electrode and extending in a first direction;
a data wiring including a first data line formed on a left side of the pixel electrode and extending in a second direction that is nonparallel to the first direction, and a second data line that is formed on a right side of the pixel electrode extending in the second direction;
a first voltage-maintaining electrode spaced apart from the first data line by a first distance along the first direction, the first voltage-maintaining electrode being electrically connected to the pixel electrode;
a second voltage-maintaining electrode spaced apart from the second data line by a second distance along the first direction, the second voltage-maintaining electrode being electrically connected to the pixel electrode;
a thin-film transistor electrically connected to the gate wiring, the data wiring and the pixel electrode; and
a storage wiring extending in the second direction across the pixel electrode, the storage wiring and the data wiring being formed from the same layer,
wherein the pixel electrode is separated from the first data line by a third distance along the first direction, and the third distance is greater than or equal to the first distance.
16. The display panel of claim 15 , wherein the second substrate further comprises a light blocking layer formed on the common electrode to cover the first and second voltage-maintaining electrodes and the data wiring.
17. A method of manufacturing an array substrate comprising:
forming a gate wiring on a base substrate along a first direction;
forming a gate insulation layer on the base substrate to cover the gate wiring;
forming a data wiring, a first voltage-maintaining electrode and a second voltage-maintaining electrode on the gate insulation layer, wherein the data wiring is formed along a second direction, the first voltage-maintaining electrode is separated from a first side of the data wiring, and the second voltage-maintaining electrode is separated from a second side of the data wiring;
forming a protection layer on the gate insulation layer to cover the data wiring and the first and second voltage-maintaining electrodes;
forming a contact hole in the protection layer to cover the first and second voltage-maintaining electrodes;
forming a pixel electrode on the protection layer to electrically connect the first and second voltage-maintaining electrodes through the contact hole;
forming a thin-film transistor electrically connected to the gate wiring, the data wiring, and the pixel electrode; and
forming the thin-film transistor with a drain electrode directly connected to at least one of the first voltage-maintaining electrode and the second voltage-maintaining electrode.
18. The array substrate of claim 1 , wherein a drain electrode of the thin-film transistor is directly connected to at least one of the first voltage-maintaining electrode and the second voltage-maintaining electrode.
19. The array substrate of claim 1 , wherein the storage wiring comprises a main wiring extending along the second direction across multiple pixel electrodes and a sub-wiring extending from the main wiring in the first direction.
20. The array substrate of claim 19 , wherein the sub-wiring covers a portion of the pixel electrode.
21. The display panel of claim 15 , wherein the thin-film transistor has a drain electrode directly connected to at least one of the first voltage-maintaining electrode and the second voltage-maintaining electrode.