Redistributed solder pads using etched lead frame
View Patent ↗A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.
1. A process for the manufacture of a semiconductor package comprising the steps of:
forming a shallow opening in a conductive lead frame body, with the bottom of said opening lying in a plane parallel to the plane of the surface of said body;
conductively and mechanically fixing the top electrode of a semiconductor die to the bottom of said opening, with the bottom electrode of said die being coplanar with said surface of said body, and with the periphery of said die spaced from the surrounding walls of said opening;
filling the annular space between the periphery of said die and the walls of said opening with an insulation material and planarizing the exposed surface of said insulation material with said surface of said body and exposing said bottom electrode of said die;
and thinning the top side of said conductive body opposite to the said receiving said opening.
2. The process of claim 1 , which includes the further step of copper plating said bottom electrode and the bottom surface of said conductive body adjacent said opening.
3. The process of claim 1 , which includes the further step of applying a redistributed contact to said bottom contact which overlaps onto the bottom surface of said insulation material.
4. The process of claim 2 , which includes the further step of applying a redistributed contact to said bottom contact which overlaps onto the bottom surface of said insulation material.
5. The process of claim 1 , wherein a plurality of said shallow openings are laterally displaced from one another and each receive a respective semiconductor die and are filled with said insulation material, thereby simultaneously to form plural die and housing assemblies; and thereafter singulating said die and housing assemblies.
6. The process of claim 2 , wherein a plurality of said shallow openings are laterally displaced from one another and each receive a respective semiconductor die and are filled with said insulation material, thereby simultaneously to form plural die and housing assemblies; and thereafter singulating said die and housing assemblies.
7. The process of claim 3 , wherein a plurality of said shallow openings are laterally displaced from one another and each receive a respective semiconductor die and are filled with said insulation material, thereby simultaneously to form plural die and housing assemblies; and thereafter singulating said die and housing assemblies.
8. The process of claim 4 , wherein a plurality of said shallow openings are laterally displaced from one another and each receive a respective semiconductor die and are filled with said insulation material, thereby simultaneously to form plural die and housing assemblies; and thereafter singulating said die and housing assemblies.