Tunable inter-digital capacitor and method of manufacturing the same
View Patent ↗Provided are a tunable inter-digital capacitor (IDC) and a method of manufacturing the same. The tunable IDC includes: a first dielectric layer formed on a substrate and having electrode pattern grooves of an IDC including a ground line and a signal line formed therein; electrode metal patterns formed in the electrode pattern grooves of the IDC including the ground line and the signal line formed in the first dielectric layer; and a second dielectric layer formed on an upper surface of the first dielectric layer to cover all of the electrode metal patterns except for parts of the ground and signal lines. Therefore, it is possible to increase tunability of the IDC and reduce drive voltage.
1. A tunable inter-digital capacitor (IDC),comprising:
a first dielectric layer formed on a substrate and having electrode pattern grooves of an IDC including a ground line and a signal line formed in the first dielectric layer;
electrode metal patterns formed in the electrode pattern grooves of the IDC including the ground line and the signal line formed in the first dielectric layer; and
a second dielectric layer formed on an upper surface of the first dielectric layer to cover all of the electrode metal patterns except for parts of the ground and signal lines.
2. The tunable IDC according to claim 1 , wherein the first and second dielectric layers are formed of a ferroelectric material or a paraelectric material.
3. The tunable IDC according to claim 1 , wherein the IDC is formed in an inter-digital pattern having a plurality of fingers formed between the ground line and the signal line, extending from the ground line and the signal line toward each other, and alternately disposed between each other at predetermined regular intervals.
4. The tunable IDC according to claim 1 , wherein the electrode metal patterns have substantially the same thickness as the depth of the electrode pattern grooves of the IDC.
5. The tunable IDC according to claim 1 , wherein the depth of the electrode pattern grooves of the IDC including the ground line and the signal line is ⅔ to ⅚ of the thickness of the first dielectric layer.