Granted Patent B2

US 7,882,383 · App. 11/789,763 · Granted Feb 1, 2011

Abstract

Claims (77)

1. A system on a chip (SOC) comprises:

a bus structure;

a processing module coupled to the bus structure;

read only memory (ROM) coupled to the bus structure;

random access memory (RAM) coupled to the bus structure;

a display interface coupled to the bus structure;

an external memory interface coupled to the bus structure;

a digital to analog conversion (DAC) module coupled to the bus structure, wherein the digital to analog converter produces an analog audio signal;

an analog to digital conversion (ADC) module coupled to the bus structure;

a headphone amplifier circuit coupled to amplify the analog audio signal;

a battery integrated circuit (IC) pin coupled to receive a battery voltage;

a real time clock module coupled to provide timing functions;

a crystal oscillation circuit coupled to produce an oscillation; and

a voltage supply circuit coupled to produce a supply voltage for at least a portion of the real time clock module and the crystal oscillation circuit, wherein the voltage supply circuit includes:

a reference circuit coupled to produce a reference voltage based on the supply voltage;

a transistor coupled to the battery IC pin, wherein the transistor produces the supply voltage based on a regulation signal and the battery voltage;

an amplifier coupled to produce the regulation signal based on the reference voltage and a feedback representation of the supply voltage; and

a start-up circuit coupled to enable the voltage supply circuit at battery connection, wherein the start-up circuit comprises:

a second transistor coupled to the battery IC pin and the transistor; and

a comparison module coupled to compare the reference voltage with a threshold, wherein, when the reference voltage compares unfavorably with the threshold, the comparison module enables the second transistor to couple the supply voltage to the battery IC pin.

2. The SOC of claim 1 , wherein the comparison module comprises:

a third transistor;

a resistor coupled to the third transistor and the battery IC pin;

an inverter coupled to the third transistor and the resistor, wherein, when the voltage reference exceeds the threshold voltage of the third transistor, the third transistor is enabled causing a first logic state at an input of the inverter and a second logic state at an output of the inverter, wherein the second logic state disables the second transistor.

3. The SOC of claim 1 , wherein the real time clock (RTC) module comprises:

an analog RTC section coupled to provide at least one of alarm generation, seconds count, persistent register storage and access, millisecond counter, and watchdog timer, wherein the analog RTC section is powered by the supply voltage;

a digital RTC section coupled to the processing module and the analog RTC section, wherein the digital RTC section retains a copy of data stored by the analog RTC section and provides updated data to the analog RTC section; and

a data transfer protection circuit coupled to the analog RTC section and the digital RTC section, wherein the data transfer protection circuit ensures accurate data transfers between the analog RTC section and the digital RTC section.

4. The SOC of claim 3 , wherein the data transfer protection circuit comprises:

a delay circuit for delaying a data transfer request to produce a delayed data transfer request; and

an AND gate coupled to AND the delayed data transfer request and a power stable indication to produce a power stable data transfer request, wherein, when the power stable indication indicates the power down condition, the power stable data transfer request disables or prevents a data transfer in a known manner.

5. A system on a chip (SOC) comprises:

a bus structure;

a processing module coupled to the bus structure;

read only memory (ROM) coupled to the bus structure;

random access memory (RAM) coupled to the bus structure;

a display interface coupled to the bus structure;

an external memory interface coupled to the bus structure;

a digital to analog conversion (DAC) module coupled to the bus structure, wherein the digital to analog converter produces an analog audio signal;

an analog to digital conversion (ADC) module coupled to the bus structure;

a headphone amplifier circuit coupled to amplify the analog audio signal;

a real time clock (RTC) module that includes:

an analog RTC section coupled to provide at least one of alarm generation, seconds count, persistent register storage and access, a millisecond counter, and a watchdog timer;

a digital RTC section coupled to the processing module and the analog RTC section, wherein the digital RTC section retains a copy of data stored by the analog RTC section and provides updated data to the analog RTC section; and

a data transfer protection circuit coupled to the analog RTC section and the digital RTC section, wherein the data transfer protection circuit ensures accurate data transfers between the analog RTC section and the digital RTC section during a power down condition, wherein the data transfer protection circuit comprises a delay circuit for delaying a data transfer request to produce a delayed data transfer request and an AND gate coupled to AND the delayed data transfer request and a power stable indication to produce a power stable data transfer request, wherein, when the power stable indication indicates the power down condition, the power stable data transfer request disables or prevents a data transfer in a known manner; and

a crystal oscillation circuit coupled to produce an oscillation.

6. The SOC of claim 5 further comprises:

a voltage supply circuit coupled to produce a supply voltage for the analog RTC section and the crystal oscillation circuit, wherein the voltage supply circuit includes:

a reference circuit coupled to produce a reference voltage based on the supply voltage;

a transistor coupled to an battery IC pin, wherein the transistor produces the supply voltage based on a regulation signal and a battery voltage received via the battery IC pin;

an amplifier coupled to produce the regulation signal based on the reference voltage and a feedback representation of the supply voltage; and

a start-up circuit coupled to enable the voltage supply circuit at battery connection.

7. The SOC of claim 6 , wherein the start-up circuit comprises:

a second transistor coupled to the battery IC pin and the transistor; and

a comparison module coupled to compare the reference voltage with a threshold, wherein, when the reference voltage compares unfavorably with the threshold, the comparison module enables the second transistor to coupled the supply voltage to the battery IC pin.

8. The SOC of claim 7 , wherein the comparison module comprises:

a third transistor;

a resistor coupled to the third transistor and the battery IC pin;

an inverter coupled to the third transistor and the resistor, wherein, when the voltage reference exceeds the threshold voltage of the third transistor, the third transistor is enabled causing a first logic state at an input of the inverter and a second logic state at an output of the inverter, wherein the second logic state disables the second transistor.

9. A voltage supply circuit coupled to produce a supply voltage for at least a portion of a real time clock module and a crystal oscillation circuit operating within a system having a battery integrated circuit (IC) pin coupled to receive a battery voltage, wherein the voltage supply circuit comprises:

a reference circuit coupled to produce a reference voltage based on the supply voltage;

a transistor coupled to the battery IC pin, wherein the transistor is configured to produce the supply voltage based on a regulation signal and the battery voltage;

an amplifier coupled to produce the regulation signal based on the reference voltage and a feedback representation of the supply voltage; and

a start-up circuit coupled to enable the voltage supply circuit at battery connection, wherein the start-up circuit comprises:

a second transistor coupled to the battery IC pin and to the transistor; and

a comparison module coupled to compare the reference voltage with a threshold, wherein, when the reference voltage compares unfavorably with the threshold, the comparison module enables the second transistor to coupled the supply voltage to the battery IC pin.

10. The voltage supply circuit of claim 9 , wherein the comparison module comprises:

a third transistor;

a resistor coupled to the third transistor and the battery IC pin;

an inverter coupled to the third transistor and the resistor, wherein, when the voltage reference exceeds the threshold voltage of the third transistor, the third transistor is enabled causing a first logic state at an input of the inverter and a second logic state at an output of the inverter, wherein the second logic state disables the second transistor.

11. The voltage supply circuit of claim 9 , wherein the real time clock (RTC) module comprises:

an analog RTC section coupled to provide at least one of alarm generation, seconds count, persistent register storage and access, a millisecond counter, and a watchdog timer, wherein the analog RTC section is powered by the supply voltage;

a digital RTC section coupled the processing module and the analog RTC section, wherein the digital RTC section retains a copy of data stored by the analog RTC section and provides updated data to the analog RTC section; and

a data transfer protection circuit coupled to the analog RTC section and the digital RTC section, wherein the data transfer protection circuit ensures accurate data transfers between the analog RTC section and the digital RTC section during a power down condition.

12. The voltage supply circuit of claim 11 , wherein the data transfer protection circuit comprises:

a delay circuit for delaying a data transfer request to produce a delayed data transfer request; and

an AND gate coupled to AND the delayed data transfer request and a power stable indication to produce a power stable data transfer request, wherein, when the power stable indication indicates the power down condition, the power stable data transfer request disables or prevents a data transfer in a known manner.

Assignments (16)