Reconfigurable signal processor
View Patent ↗A reduction in circuit size and in power consumption is provided. A signal processor includes: processor elements 501 , which are mapped by circuit reconfiguration; processor elements 502 a and 502 b , which are not mapped by circuit reconfiguration; a power voltage supply area 503 ; a power voltage cutoff area 504 ; a system control CPU 505 ; a configuration information storage memory 506 ; a configuration control signal decoder 507 ; a configuration control circuit 508 ; a configuration control circuit 509 for a power supply unit; a data memory 510 ; a global bus (high voltage side) 511 ; and a global bus switch (high voltage side) 512 . The signal processor includes a function for circuit reconfiguration of the individual processor elements 501 in consonance with the contents of a signal process to be performed and a function for changing a voltage to be supplied to the processor elements 501.
1. A signal processor comprising:
a plurality of processor elements, each including a computing unit, an input register disposed at an input portion of the computing unit and an output register disposed at an output portion of the computing unit;
a bus, for connecting the plurality of processor elements;
a switch unit, for changing a connection for the bus;
a control circuit, for controlling the switch unit in accordance with software; and
a memory, for storing scheduling information relating to an order to perform signal processes by the processor elements,
wherein the signal processor is configured to operate in:
a first operating mode, during which the processor elements sequentially perform signal processes; and
a second operating mode, during which signal processes performed by the processor elements and a data transfer process from the output registers of the processor elements to the input registers are alternately performed, and connections for the plurality of processor elements are changed during a period in which the processor elements perform the signal processes, and
the control circuit performs circuit reconfiguration in a time-sharing manner in accordance with the scheduling information.