Hardware-efficient searcher architecture for code division multiple access (CDMA) cellular receivers

1. An apparatus comprising:

a receiver for receiving a multipath signal; and

a searcher that stores delayed samples of the received multipath signal;

wherein the searcher is operative on the delayed samples of the received multipath signal for identifying one or more paths of the received multipath signal;

wherein the searcher comprises:

a shift register for storing J sub-chip delayed samples of the received multipath signal;

a number of descramblers for correlating at least some of the stored J sub-chip delayed samples of the received multipath signal with a portion of a scrambling code over a chip interval, such that (a) N of the J sub-chip delayed samples are correlated at a time with the portion of the scrambling code, where J>N>1, and (b) J output values are provided over the chip interval, wherein each descrambler uses the same portion of the scrambling code; and

an integrator for accumulating each of the J output values from the number of descramblers over a dwell period, wherein the dwell period comprises more than one chip interval.

2. The apparatus of claim 1 , wherein the apparatus is user equipment (UE) of a code division multiple access (CDMA)-based wireless network.

3. The apparatus of claim 1 , wherein the portion of the scrambling code used by the number of descramblers changes every chip interval.

4. The apparatus of claim 1 , further comprising a memory for storing the scrambling code and for providing the same portion of the scrambling code.

5. The apparatus of claim 4 , wherein the scrambling code is stored in the memory with a scrambling code value of “+1” represented by a first binary value and a scrambling code value of “−1” represented by a second binary value.

6. The apparatus of claim 5 , wherein each of the number of descramblers includes logic for selectively changing a sign of a sample in accordance with a corresponding scrambling code value.

7. A method for use in a receiver, the method comprising:

receiving a multipath signal;

storing J sub-chip delayed samples of the received multipath signal; and

operating on the stored delayed samples of the received multipath signal for identifying one or more paths of the received signal;

wherein the operating step includes the steps of:

correlating at least some of the stored J sub-chip delayed samples of the received multipath signal with a portion of a scrambling code over a chip interval, such that (a) N of the J sub-chip delayed samples are correlated at a time with the portion of the scrambling code, where J>N>1, and (b) J output values are provided over the chip interval, wherein each correlation uses the same portion of the scrambling code; and

accumulating each of the J output values resulting from performance of the correlating step over a dwell period, wherein the dwell period comprises more than one chip interval.

8. The method of claim 7 , wherein the receiver is user equipment (UE) of a code division multiple access (CDMA)-based wireless network.

9. The method of claim 7 , wherein the portion of the scrambling code changes every chip interval.

10. The method of claim 7 , further comprising the step of storing the scrambling code in a memory for providing the same portion of the scrambling code.

11. The method of claim 10 , wherein the scrambling code is stored in the memory with a scrambling code value of “+1” represented by a first binary value and a scrambling code value of “−1” represented by a second binary value.

12. The method of claim 11 , wherein each correlation includes selectively changing a sign of a sample in accordance with a corresponding scrambling code value.