Optical transmitter circuit
View Patent ↗A light emitting element driving differential switch ( 2 ) includes first and second transistors (M 1 , M 2 ). A third transistor (M 3 ) is connected as an auxiliary switch in parallel to the first transistor (M 1 ) whose drain is connected to a light emitting element ( 1 ). A third switch driving signal (IN 3 ) is input to the third transistor (M 3 ) to turn ON the third transistor (M 3 ) at a slightly earlier point in time than when complementary switch driving signals (IN 1 , IN 2 ) are input to the first and second transistors (M 1 , M 2 ) to drive the first and second transistors (M 1 , M 2 ). This improves the rising characteristics of the output from the light emitting element having a high power level.
1. An optical transmitter circuit, comprising:
a light emitting element;
a light emitting element driving differential switch including a first transistor whose drain is connected to the light emitting element and a second transistor whose source is connected to a source of the first transistor;
a third transistor whose drain and source are connected to the drain and the source of the first transistor, respectively;
a modulation current source connected to sources of the first, second and third transistors;
a bias current source for supplying a bias current to the light emitting element; and
switch driving circuits, each of which drives one of the first, second and third transistors.
2. The optical transmitter circuit of claim 1 , wherein a signal for driving the third transistor is input at a point in time earlier than signals for driving the first and second transistors.
3. The optical transmitter circuit of claim 1 , wherein a signal for driving the third transistor has an amplitude different from that of at least one of the signals for driving the first and second transistors.
4. The optical transmitter circuit of claim 3 , wherein the signal for driving the third transistor has a greater amplitude than those of the signals for driving the first and second transistors.
5. The optical transmitter circuit of claim 1 , wherein a capacity of the switch driving circuit for driving the third transistor is different from at least one of those for driving the first and second transistors.
6. The optical transmitter circuit of claim 5 , wherein a capacity of the switch driving circuit for driving the third transistor is greater than those for driving the first and second transistors.
7. The optical transmitter circuit of claim 1 , wherein a signal for driving the third transistor has a DC voltage level different from that of at least one of signals for driving the first and second transistors.
8. The optical transmitter circuit of claim 7 , wherein the signal for driving the third transistor has a DC voltage level higher than those of the signals for driving the first and second transistors.
9. The optical transmitter circuit of claim 1 , wherein a signal for driving the third transistor has a duty different from that of at least one of signals for driving the first and second transistors.
10. The optical transmitter circuit of claim 9 , wherein the signal for driving the third transistor has a high-level period longer than those of the signals for driving the first and second transistors.
11. The optical transmitter circuit of one of claims 1 , 2 , 3 , 5 , 7 and 9 , wherein a signal for driving the second transistor is connected to a fixed voltage.
12. An optical transmitter circuit, comprising:
a light emitting element;
a light emitting element driving differential switch including a first transistor whose drain is connected to the light emitting element and a second transistor whose source is connected to a source of the first transistor;
a third transistor whose drain and source are connected to the drain and the source of the first transistor, respectively;
a modulation current source connected to sources of the first, second and third transistors; and
a bias current source for supplying a bias current to the light emitting element.
13. The optical transmitter circuit of one of claims 1 , 2 , 3 , 5 , 7 , 9 and 12 , wherein a sum of a size of the first transistor and that of the third transistor is greater than a size of the second transistor.