IP Library Granted Patent US 8,051,355
Granted Patent B2
US 8,051,355 · App. 11/794,446 · Granted Nov 1, 2011

Multilevel low density parity-check coded modulation

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,051,355
App. No.
11/794,446
Granted
Nov 1, 2011
Kind
B2
Abstract

A method and apparatus are provided for encoding and decoding a communication signal. Processes for encoding and decoding the communication signal use a first low density parity-check code (LDPC) construction and a second low density parity-check code construction that differs from the first low density parity-check code construction. Multilevel coding (MLC) is applied to protect each address bit of a signal point by an individual LDPC code. In one embodiment, the first level is coded with a progressive edge-growth LDPC code, the second level is coded with a Reed-Solomon LDPC code and the third level is left uncoded.

Claims (65)

1. A method comprising:

partitioning a data block into a plurality of sub-blocks;

encoding a first sub-block using a first low density parity-check code construction such that a first codeword is formed;

encoding a second sub-block using a second low density parity-check code construction such that a second codeword is formed;

mapping the first codeword, the second codeword, and bits of an uncoded sub-block forming a signal to transmit into a communication channel using a transmitter, the mapping conducted such that each bit of the uncoded codeword selects a symbol of an alphabet from the mapping of the first codeword and the second codeword to provide the signal as a block of alphabet symbols, wherein the first low density parity-check code construction differs from the second low density parity-check code construction.

2. The method of claim 1 , wherein using a first low density parity-check code construction includes selecting the first low density parity-check code construction with respect to bit-error degradation for low signal-to-noise ratios and using a second low density parity-check code construction includes selecting the second low density parity-check code construction with respect to avoiding an error floor.

3. The method of claim 1 , wherein using a first low density parity-check code construction includes using a Progressive Edge Growth code construction.

4. The method of claim 1 , wherein using a second low density parity-check code construction includes using a Reed Solomon low density parity-check code construction.

5. The method of claim 1 , wherein the method further includes:

partitioning a PAM constellation into two 4-level cosets with a Progressive Edge Growth code construction to select one of the two 4-level cosets, the Progressive Edge Growth code construction being the first low density parity-check code construction; and

partitioning each 4-level coset into two 2-level co-cosets with a Reed Solomon low density parity-check code construction used to select one of the two 2-level co-cosets, the Reed Solomon low density parity-check code construction being the second low density parity-check code construction.

6. The method of claim 1 , wherein the method is a multilevel coding process using the first and second low density parity-check code constructions.

7. A method comprising:

decoding a signal using a first low density parity-check code construction providing a first codeword, the signal received from a communication channel using a receiver;

decoding the signal using a second low density parity-check code construction and the first codeword providing a second codeword, wherein the first low density parity-check code construction differs from the second low density parity-check code construction;

extracting bits from the signal to provide a third codeword, the extracted bits corresponding to uncoded bits used to provide code modulation at a transmitting end, the bits extracted using encoding information obtained from decoding the signal using the first low density parity-check code construction and from decoding the signal using the second low density parity-check code construction and the first codeword, and

providing a completed message from a sum of message bits in each of the first codeword, the second codeword, and the third codeword.

8. The method of claim 7 , wherein using a first low density parity-check code construction includes using a Progressive Edge Growth code construction, and using a second low density parity-check code construction includes using a Reed Solomon low density parity-check code construction.

9. The method of claim 7 , wherein the method is a multistage decoding process using the first and second low density parity-check code constructions.

10. A computer readable device that stores instructions, which when performed by a machine, cause the machine to:

partition a data block into a plurality sub-blocks;

encode a first sub-block using a first low density parity-check code construction to form a first codeword;

encode a second sub-block using a second low density parity-check code construction to form a second codeword;

map the first codeword, the second codeword, and bits of an uncoded sub-block to form a signal such that each bit of the uncoded codeword selects a symbol of an alphabet from the mapping of the first codeword and the second codeword to provide the signal as a block of alphabet symbols, wherein the first low density parity-check code construction differs from the a second low density parity-check code construction.

11. The computer-readable device of claim 10 , wherein the first low density parity-check code construction includes a Progressive Edge Growth code construction and the second low density parity-check code construction includes a Reed Solomon low density parity-check code construction.

12. The computer-readable medium device of claim 10 , wherein to partition a data block includes:

partitioning a PAM constellation into two 4-level cosets with a Progressive Edge Growth code construction to select one of the two 4-level cosets, the Progressive Edge Growth code construction being the first low density parity-check code construction; and

partitioning each 4-level coset into two 2-level co-cosets with a Reed Solomon low density parity-check code construction used to select one of the two 2-level co-cosets, the Reed Solomon low density parity-check code construction being the first low density parity-check code construction.

13. A computer-readable device that stores instructions, which when performed by a machine, cause the machine to:

decode the signal using a first low density parity-check code construction to provide a first codeword;

decode the signal using a second low density parity-check code construction and the first codeword to provide a second codeword, wherein the first low density parity-check code construction differs from the a second low density parity-check code construction;

extract bits from the signal to provide a third codeword, the extracted bits corresponding to uncoded bits used to provide code modulation at a transmitting end, the bits extracted using encoding information obtained from decoding the signal using the first low density parity-check code construction and from decoding the signal using the second low density parity-check code construction and the first codeword, and

provide a completed message from a sum of message bits in each of the first codeword, the second codeword, and the third codeword.

14. The computer-readable device of claim 13 , wherein the first low density parity-check code construction includes a Progressive Edge Growth code construction.

15. The computer-readable device of claim 13 , wherein the second low density parity-check code construction includes a Reed Solomon low density parity-check code construction.

16. An apparatus comprising:

an encoder to encode data partitioned into a plurality of sub-blocks, the encoder having a first low density parity-check code construction to encode a first sub-block to form a first codeword and having a second low density parity-check code construction to encode a second sub-block to form a second codeword, wherein the first low density parity-check code construction differs from the second low density parity-check code construction; and

a mapper to map the first codeword, the second codeword, and bits of an uncoded sub-block to form a signal such that each bit of the uncoded codeword selects a symbol of an alphabet from the mapping of the first codeword and the second codeword to provide the signal as a block of alphabet symbols.

17. The apparatus of claim 16 , wherein the first low density parity-check code construction includes a Progressive Edge Growth code construction and the second low density parity-check code construction includes a Reed Solomon low density parity-check code construction.

18. The apparatus of claim 16 , wherein the encoder is adapted to partition a PAM constellation into two 4-level cosets with a Progressive Edge Growth code construction to select one of the two 4-level cosets, and partition each 4-level coset into two 2-level co-cosets with a Reed Solomon low density parity-check code construction to select one of the two 2-level co-cosets, the Progressive Edge Growth code construction being the first low density parity-check code construction and the Reed Solomon low density parity-check code construction being the second low density parity-check code construction.

19. An apparatus comprising:

a decoder to decode a signal from a communication channel to provide decoded data, the decoder having a first low density parity-check code construction to provide a first codeword and a second low density parity-check code construction to provide a second codeword from the first codeword and the signal, wherein the first low density parity-check code construction differs from the a second low density parity-check code construction, the decoder configured to extract bits from the signal to provide a third codeword, the extracted bits corresponding to uncoded bits used to provide code modulation at a transmitting end, the bits operatively extracted using encoding information obtained from decoding the signal using the first low density parity-check code construction and from decoding the signal using the second low density parity-check code construction and the first codeword, the decoder arranged to provide a completed message from a sum of message bits in each of the first codeword, the second codeword, and the third codeword.

20. The apparatus of claim 19 , wherein the first low density parity-check code construction includes a Progressive Edge Growth code construction.

21. The apparatus of claim 19 , wherein the second low density parity-check code construction includes a Reed Solomon low density parity-check code construction.

22. A system comprising:

an encoder to encode data partitioned into a plurality of sub-blocks, the encoder having a first low density parity-check code construction to encode a first sub-block to form a first codeword and having a second low density parity-check code construction to encode a second sub-block to form a second codeword, wherein the first low density parity-check code construction differs from the a second low density parity-check code construction;

a mapper to map the first codeword, the second codeword, and bits of an uncoded sub-block to form a signal such that each bit of the uncoded codeword selects a symbol of an alphabet from the mapping of the first codeword and the second codeword to provide the signal as a block of alphabet symbols;

a transmitter to transmit the signal; and

a network interface having connections to couple the transmitter to a wired network.

23. The system of claim 22 , wherein the first low density parity-check code construction includes a Progressive Edge Growth code construction and the second low density parity-check code construction includes a Reed Solomon low density parity-check code construction.

24. The system of claim 22 , wherein the network interface includes a network interface card.

25. The system of claim 22 , wherein the network interface is compliant with 10GBase-T.

26. The system of claim 22 , wherein the system further includes at least one of a computer, a switch, a router, or a server.

27. The system of claim 26 , wherein the system further includes connections to the at least one of a computer, a switch, a router, or a server that are compatible with PCI.

28. The system of claim 26 , wherein the system further includes connections to the at least one of a computer, a switch, a router, or a server that are compatible with PCI express.

29. A system comprising:

a receiver to receive a signal from a communication channel;

a decoder to decode the signal to provide decoded data, the decoder having a a first low density parity-check code construction to provide a first codeword and a second low density parity-check code construction to provide a second codeword from the first codeword and the signal, wherein the first low density parity-check code construction differs from the a second low density parity-check code construction, the decoder configured to extract bits from the signal to provide a third codeword, the extracted bits corresponding to uncoded bits used to provide code modulation at a transmitting end, the bits operatively extracted using encoding information obtained from decoding the signal using the first low density parity-check code construction and from decoding the signal using the second low density parity-check code construction and the first codeword, the decoder arranged to provide a completed message from a sum of message bits in each of the first codeword, the second codeword, and the third codeword; and

a network interface having connections to couple the receiver to a wired network.

30. The system of claim 29 , wherein the first low density parity-check code construction includes a Progressive Edge Growth code construction and the second low density parity-check code construction includes a Reed Solomon low density parity-check code construction.

31. The system of claim 29 , wherein the network interface includes a network interface card.

32. The system of claim 29 , wherein the network interface is compliant with 10GBase-T.

33. The system of claim 29 , wherein the system further includes at least one of a computer, a switch, a router, or a server.

34. The system of claim 33 , wherein the system further includes a connection to the at least one of a computer, a switch, a router, or a server that is compatible with PCI.

35. The system of claim 33 , wherein the system further includes a connection to the at least one of a computer, a switch, a router, or a server that is compatible with PCI express.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072915/0599 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2008
From: TAUBIN, FELIX ALEKSANDROVICH; BELOGOLOVY, ANDREY VLADIMIROVICH; KOZLOV, ALEKSANDR V.
To: INTEL CORPORATION
Reel/Frame 021610/0568 →
Continuity (1)
Related Publication 20080320362A1 · Dec 25, 2008