IP Library › Patent Application 11797255
Patent Application
App. No. 11/797,255

Semiconductor memory device including an SOI substrate

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Quick Facts
Patent No.
US None
App. No.
11/797,255
Abstract

A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Claims (5)

1 - 36 . (canceled)

37 . A semiconductor memory device comprising at least one first semiconductor element and at least one second semiconductor element,

wherein an element isolation film for isolating said first semiconductor element and said second semiconductor element from each other is formed on an SOI substrate,

wherein said element isolation film is in contact with an insulation film in said SOI substrate.

38 - 43 . (canceled)