Semiconductor integrated circuit
View Patent ↗A plurality of memory macros, to which first power is supplied, and a logic circuit block, to which second power is supplied, are provided. The memory macros are collectively disposed as a memory block on a semiconductor chip, and memory power wires for supplying the first power to the memory macros that form the memory block are provided over the memory block.
1. A semiconductor integrated circuit comprising:
a plurality of memory macros, to which first power is supplied;
a logic circuit block, to which second power is supplied;
an input terminal for supplying the first power; and
a plurality of memory power wires provided over the plurality of memory macros,
wherein the plurality of memory macros are collectively disposed as a memory block on a semiconductor chip, and
the input terminal is connected to at least two of the memory macros through at least one of the memory power wires.
2. The semiconductor integrated circuit of claim 1 , wherein the memory block is formed of all of the memory macros.
3. The semiconductor integrated circuit of claim 1 , wherein the memory power wires are formed in a mesh in a plurality of wiring layers.
4. The semiconductor integrated circuit of claim 3 , wherein bit lines of the memory macros are in the same direction and word lines of the memory macros are in the same direction.
5. The semiconductor integrated circuit of claim 4 , wherein the memory macros that form the memory block are arranged in a matrix, and
at least either the number of bit lines or the number of word lines of each of the memory macros is the same.
6. The semiconductor integrated circuit of claim 5 , wherein an input/output terminal of each of the memory macros is disposed on a side of the memory block that faces the logic circuit block.
7. The semiconductor integrated circuit of claim 6 , wherein the input/output terminals correspond to the memory power wires and are formed in a plurality of wiring layers.
8. The semiconductor integrated circuit of claim 1 , further comprising a power circuit macro for generating fourth power based on third power which is input from outside the semiconductor integrated circuit and supplying the fourth power to the memory macros,
wherein the power circuit macro is provided in a one-to-one correspondence with the memory block, and
internal power wires for supplying the fourth power to the memory macros are formed over the memory block.
9. The semiconductor integrated circuit of claim 8 , wherein the power circuit macro is disposed between the memory block and a power terminal to which the first power is input.
10. The semiconductor integrated circuit of claim 8 , wherein the power circuit macro is disposed between the memory block and a power terminal to which the third power is input.
11. The semiconductor integrated circuit of claim 8 , wherein the power circuit macro includes:
a power generation circuit block for generating power based on the third power; and
a smoothing capacitor block for suppressing voltage variation in the power generated by the power generation circuit block.
12. The semiconductor integrated circuit of claim 8 , wherein a side of the memory block and a side of the power circuit macro that face each other have substantially the same length.
13. The semiconductor integrated circuit of claim 8 , wherein the memory block and the power circuit macro are substantially adjacent to each other.
14. The semiconductor integrated circuit of claim 1 , wherein the first power and the second power are not the same.
15. A semiconductor integrated circuit comprising:
a plurality of memory macros, to which first power is supplied;
a logic circuit block, to which second power is supplied;
wherein the plurality of memory macros are collectively disposed as a memory block on a semiconductor chip, and
memory power wires for supplying the first power to the memory macros that form the memory block are provided over the memory block,
wherein the semiconductor integrated circuit further comprises a power circuit macro for generating fourth power based on third power which is input from outside the semiconductor integrated circuit and supplying the fourth power to the memory macros,
wherein the power circuit macro is provided in a one-to-one correspondence with the memory block, and
internal power wires for supplying the fourth power to the memory macros are formed over the memory block.
16. The semiconductor integrated circuit of claim 15 , wherein the power circuit macro includes:
a power generation circuit block for generating power based on the third power; and
a smoothing capacitor block for suppressing voltage variation in the power generated by the power generation circuit block.
17. The semiconductor integrated circuit of claim 15 , wherein a side of the memory block and a side of the power circuit macro that face each other have substantially the same length.
18. The semiconductor integrated circuit of claim 15 , wherein the memory block and the power circuit macro are substantially adjacent to each other.
19. The semiconductor integrated circuit of claim 15 , wherein the power circuit macro is disposed between the memory block and a power terminal to which the third power is input.