Semiconductor device with electric fuse having a flowing-out region

1. A semiconductor device, comprising:

a semiconductor substrate; and

an electric fuse formed on said semiconductor substrate and composed of an electric conductor,

wherein said electric fuse includes a first interconnect, a via coupled to said first interconnect and a second interconnect coupled to said via, which are formed in different layers, respectively, in a condition before cutting said electric fuse, and

said electric fuse comprises a void region formed between said first interconnect and said via or in said via, and a flowing-out region formed of said electric conductor flowing in a direction away from a periphery of said second interconnect and away from the void region, in a condition after cutting said electric fuse.

2. The semiconductor device as set forth in claim 1 , wherein said electric conductor is composed of a copper-containing metallic film, which contains copper as a major constituent.

3. The semiconductor device as set forth in claim 2 ,

wherein said electric fuse further includes a first barrier metal film provided between said first interconnect and said via such that said first barrier metal film is provided in contact with said first interconnect and said via, in said condition before cutting said electric fuse, and

wherein said void region is formed between said first barrier metal film and said first interconnect, in said condition after cutting said electric fuse.

4. The semiconductor device as set forth in claim 3 ,

wherein said electric fuse further includes a second barrier metal film on side surface of said second interconnect such that said second barrier metal film is provided in contact with said second interconnect, in said condition before cutting said electric fuse,

wherein a crack is created in said second barrier metal film and said flowing-out region is formed of said electric conductor flowed from said crack, in said condition after cutting said electric fuse.

5. The semiconductor device as set forth in claim 2 ,

wherein said electric fuse further includes a second barrier metal film on a side surface of said second interconnect such that said second barrier metal film is provided in contact with said second interconnect, in said condition before cutting said electric fuse,

wherein a crack is created in said second barrier metal film and said flowing-out region is formed of said electric conductor flowed from said crack, in said condition after cutting said electric fuse.

6. The semiconductor device as set forth in claim 1 , wherein said second interconnect is formed to have an area along a direction in a surface of said semiconductor substrate, which is larger than that of said first interconnect.

7. The semiconductor device as set forth in claim 1 , further comprising an insulating layer formed in a periphery of said electric fuse on said semiconductor substrate,

wherein said second interconnect is formed in an interconnect trench formed in said insulating layer, and

wherein said flowing-out region is formed of said electric conductor flowed outside of said interconnect trench.

8. The semiconductor device as set forth in claim 1 , further comprising an insulating layer formed in a periphery of said electric fuse on said semiconductor substrate,

wherein said insulating layer includes a first insulating layer formed in a periphery of said via and a second insulating layer formed in a periphery of said second interconnect, said second insulating layer having a Young's modulus lower than that of said first insulating layer.

9. The semiconductor device as set forth in claim 8 , wherein said second interconnect is formed in an interconnect trench formed in said second insulating layer, and wherein said flowing-out region is formed of said electric conductor flowed outside of said interconnect trench.

10. The semiconductor device as set forth in claim 1 , further comprising an insulating layer formed in a periphery of said electric fuse on said semiconductor substrate,

wherein said insulating layer includes a first insulating layer formed in a periphery of said via and a second insulating layer formed in a periphery of said second interconnect, said second insulating layer having a film density lower than that of said first insulating layer.

11. The semiconductor device as set forth in claim 10 , wherein said second interconnect is formed in an interconnect trench formed in said second insulating layer, and wherein said flowing-out region is formed of said electric conductor flowed outside of said interconnect trench.

12. The semiconductor device as set forth in claim 1 , further comprising an insulating layer formed in a periphery of said electric fuse on said semiconductor substrate,

wherein said insulating layer includes a first insulating layer formed in a periphery of said via and a second insulating layer formed in a periphery of said second interconnect, said second insulating layer having a dielectric constant lower than that of said first insulating layer.

13. The semiconductor device as set forth in claim 12 , wherein said second interconnect is formed in an interconnect trench formed in said second insulating layer, and wherein said flowing-out region is formed of said electric conductor flowed outside of said interconnect trench.

14. A semiconductor device, comprising:

a semiconductor substrate; and

an electric fuse formed on said semiconductor substrate and composed of an electric conductor, wherein,

in a first pre-cut condition of said electric fuse, said electric fuse comprises a first interconnect located on semiconductor layer, a second interconnect located on a second semiconductor layer, and a via coupling the first and second interconnects, the via located on a third semiconductor layer located between the first and second semiconductor layers,

in a second post-cut condition of said fuse, said electric fuse further comprises a void region and a flowing-out region, said void region and said flowing-out region formed after cutting said fuse, said void region being intermediate said first interconnect and said via, said flowing out region being adjacent a terminal periphery end of said second interconnect, and

in the first pre-cut condition of said electric fuse, said electric fuse being free of said void region and said flowing-out region.