Semiconductor device
View Patent ↗In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.
1. A semiconductor device comprising:
a first memory cell;
a second memory cell;
a first bit line connected to the first memory cell;
a second bit line connected to the second memory cell;
a word line connected to the first memory cell and the second memory cell;
a source line connected to the first memory cell and the second memory cell;
a sense amplifier connected to the first bit line and the second bit line;
a first transistor of which one of a first source and a first drain is connected to the first bit line;
a second transistor of which one of a second source and a second drain is connected to the first bit line;
a third transistor of which one of a third source and a third drain is connected to the second bit line; and
a fourth transistor of which one of a fourth source and a fourth drain is connected to the second bit line,
wherein the first memory cell comprises a fifth transistor and a first variable resistive element,
wherein the second memory cell comprises a sixth transistor and a second variable resistive element,
wherein the first transistor and the third transistor are for supplying a first voltage to the first bit line and the second bit line, respectively, and the second transistor and the fourth transistor are for supplying a second voltage to the first bit line and the second bit line, respectively,
wherein when the first memory cell is a selected memory cell to read information stored in the first memory cell in a read operation period, the first voltage is supplied to the first bit line by setting the first transistor ON, and
wherein the second voltage is a voltage of the source line, and the second voltage is supplied to the second bit line by setting the fourth transistor ON while the first transistor is set ON in the read operation period.
2. The semiconductor device according to claim 1 ,
wherein the voltage of the second bit line is 0V in the read operation period.
3. The semiconductor device according to claim 1 ,
wherein the fifth transistor is coupled to the sense amplifier via the first bit line and the sixth transistor is coupled to the sense amplifier via the second bit line, and
wherein the fifth transistor and the sixth transistor are set OFF while the first transistor is set ON.
4. The semiconductor device according to claim 1 , further comprising a write driver connected to the first bit line and the second bit line.
5. The semiconductor device according to claim 1 ,
wherein gate electrodes of the fifth and sixth transistors are connected to the word line.
6. The semiconductor device according to claim 5 ,
wherein the first transistor is set OFF after the first voltage is applied to the first bit line, and the word line is supplied with an activation voltage to set the fifth and sixth transistors ON after the first transistor is set OFF, and
wherein the fourth transistor is set ON while the word line is being supplied with the activation voltage.
7. The semiconductor device according to claim 5 ,
wherein one of a source and a drain of the fifth transistor is connected to the source line, the other of the source and the drain of the fifth transistor is connected to one side of the first variable resistive element, and another side of the first variable resistive element is connected to the first bit line, and
wherein one of a source and a drain of the sixth transistor is connected to the source line, the other of the source and the drain of the sixth transistor is connected to one side of the second variable resistive element, and another side of the second variable resistive element is connected to the second bit line.
8. The semiconductor device according to claim 7 ,
wherein each of the first and second variable resistive elements comprises chalcogenide material.
9. The semiconductor device according to claim 5 ,
wherein one of a source and a drain of the fifth transistor is connected to the first bit line, the other of the source and the drain of the fifth transistor is connected to one side of the first variable resistive element, and another side of the first variable resistive element is connected to the source line, and
wherein one of a source and a drain of the sixth transistor is connected to the second bit line, the other of the source and the drain of the sixth transistor is connected to one side of the second variable resistive element, and another side of the second variable resistive element is connected to the source line.
10. The semiconductor device according to claim 9 ,
wherein each of the first and second variable resistive elements comprises chalcogenide material.