Method for fabricating a thin film transistor

1. A method for fabricating a thin film transistor comprising:

providing the thin film transistor that includes a substrate, a buffer layer, an activation layer formed on said buffer layer, and a gate insulation layer formed on said buffer layer and said activation layer, with said buffer layer having a step formed between a lower part of said activation layer and a part except said lower part of said activation layer, and said step being up to a half of the thickness sum of said activation layer and gate insulation layer;

forming a polycrystalline silicon layer;

forming the activation layer by etching said polycrystalline silicon layer;

treating a surface of said activation layer; and

depositing the gate insulation layer on said substrate,

with etching time being controlled in the activation layer forming process and the activation layer surface treatment process to accommodate the step between a lower part of a gate in said buffer layer and a part except the lower part of said gate having a step value corresponding up to a half of the thickness sum of said activation layer and gate insulation layer.

2. The method for fabricating a thin film transistor according to claim 1 , wherein the etching time is controlled to accommodate said buffer layer including the step to such a degree where said gate insulation layer is deposited to an even thickness on a side wall of said activation layer.

3. The method for fabricating a thin film transistor according to claim 1 , wherein the etching time is controlled to accommodate said buffer layer having a step corresponding up to half of the thickness sum of the activation layer and gate insulation layer.

4. The method for fabricating a thin film transistor according to claim 1 , wherein a thickness of said gate insulation layer is at least 400 Å when the thickness of solid-phase crystallization polysilicon is 300 Å and the step is 350 Å in the activation layer or the thickness of said gate insulation layer is at least 1,000 Å when the thickness of excimer laser annealing polysilicon is 500 Å and the step is 750 Å in said activation layer.

5. A method of fabricating a thin film transistor, comprising:

depositing an amorphous silicon layer on a substrate equipped with a buffer layer;

forming a polycrystalline silicon layer by crystallizing said amorphous silicon layer;

forming an activation layer by etching said polycrystalline silicon layer;

treating a surface of said activation layer; and

depositing a gate insulation layer on said substrate, wherein a step between a lower part of gate in the buffer layer and a part except the lower part of said gate has a step value corresponding to a half or less of the thickness sum of said activation layer and gate insulation layer by controlling an etching time in said activation layer forming process and said activation layer surface treatment process.

6. The method of claim 5 , wherein said buffer layer has a step to such a degree that a thickness of said gate insulation layer is not changed on said side wall of said buffer layer by controlling the etching time.

7. The method of claim 5 , wherein said buffer layer having a step corresponding to a half or less of the thickness sum of the activation layer and gate insulation layer is accommodated by controlling said etching time.

8. The method of claim 5 , wherein a thickness of said gate insulation layer is 400 Å or more upon thickness of SPC polysilicon is 300 Å and the step is 350 Å in said activation layer.

9. The method of claim 5 , wherein thickness of said gate insulation layer is 1,000 Å or more upon the thickness of ELA polysilicon is 500 Å and the step is 750 Å in said activation layer.

10. The method of claim 7 , wherein said buffer layer has a step to such a degree that thickness of said gate insulation layer is not changed on said side wall of said buffer layer by controlling said etching time.

11. A method of fabricating a thin film transistor, comprising:

providing a substrate;

forming a polycrystalline silicon layer;

forming an activation layer by etching said polycrystalline silicon layer;

treating a surface of said activation layer; and

depositing a gate insulation layer on said substrate,

wherein a step between a lower part of a gate in said buffer layer and a part except the lower part of said gate having a step value corresponding up to a half of the thickness sum of said activation layer and gate insulation layer by controlling an etching time in the activation layer forming process and activation layer surface treatment process.

12. The method of claim 11 , wherein said buffer layer including the step is accommodated to such a degree where said gate insulation layer is deposited to an even thickness on a side wall of said activation layer by controlling the etching time.

13. The method of claim 11 , said buffer layer having a step corresponding up to half of the thickness sum of the activation layer and gate insulation layer is accommodated by controlling the etching time.

14. The method of claim 11 , wherein a thickness of said gate insulation layer is at least 400 Å upon the thickness of SPC polysilicon is 300 Å and the step is 350 Å in the activation layer or the thickness of said gate insulation layer is at least 1,000 Å upon the thickness of ELA polysilicon is 500 Å and the step is 750 Å in said activation layer.