Method of designing semiconductor device

1. A method of designing a semiconductor device using design program recorded on a non-transitory computer-readable medium, comprising:

(A) dividing a layout region of a semiconductor chip into matrix by a unit region;

(B) determining an interconnection layout such that an occupation ratio of a high-density region to said layout region is less than 50%, said high-density region being a set of said unit region in which interconnection density is higher than a predetermined reference value; and

(C) dividing said high-density region into a plurality of divided high-density regions and modifying said interconnection layout by distributing said plurality of divided high-density regions to said layout region.

2. The method according to claim 1 , wherein said unit region is a square whose length on a side is smaller than a width of a scribe line.

3. The method according to claim 1 , wherein said (B) step includes:

(b1) determining a provisional interconnection layout;

(b2) calculating interconnection density of said provisional interconnection layout in said unit region;

(b3) determining said high-density region by extracting said unit region in which said calculated interconnection density is higher than said predetermined reference value;

(b4) calculating an occupation ratio of said determined high-density region to said layout region;

(b5) executing said (b1) to (b4) steps again, if said calculated occupation ratio is equal to or more than 50%; and

(b6) determining said provisional interconnection layout as said interconnection layout, if said calculated occupation ratio is less than 50%.

4. The method according to claim 1 , wherein in said (C) step, said plurality of divided high-density regions are placed in a stripe pattern.

5. The method according to claim 4 , wherein an interval between two adjacent divided high-density regions of said plurality of divided high-density regions is larger than a width of a scribe line.

6. The method according to claim 1 , wherein said (C) step includes:

(c1) dividing said layout region into a plurality of strip regions, wherein a longitudinal direction of each of said plurality of strip regions is a first direction and said plurality of strip regions align in a second direction orthogonal to said first direction;

(c2) dividing said high-density region into said plurality of divided high-density regions such that a width of each of said plurality of divided high-density regions in said second direction is smaller than a width of said each strip region in said second direction; and

(c3) placing said plurality of divided high-density regions in respective strip regions among said plurality of strip regions.

7. The method according to claim 6 , wherein in said (c3) step, said plurality of divided high-density regions are placed in at least every other strip region with respect to said plurality of strip regions.

8. The method according to claim 6 , wherein in said (c1) step, said layout region is divided by lines equally spaced from an edge towards said second direction.

9. The method according to claim 8 , wherein said width of said each strip region in said second direction is equal to a width of a scribe line.

10. A design program recorded on a non-transitory computer-readable medium that, when executed, causes a computer to perform a process comprising:

(A) dividing a layout region of a semiconductor chip into matrix by a unit region;

(B) determining an interconnection layout such that an occupation ratio of a high-density region to said layout region is less than 50%, said high-density region being a set of said unit region in which interconnection density is higher than a predetermined reference value; and

(C) dividing said high-density region into a plurality of divided high-density regions and modifying said interconnection layout by distributing said plurality of divided high-density regions to said layout region.

11. The design program according to claim 10 , wherein said (B) step includes:

(b1) determining a provisional interconnection layout;

(b2) calculating interconnection density of said provisional interconnection layout in said unit region;

(b3) determining said high-density region by extracting said unit region in which said calculated interconnection density is higher than said predetermined reference value;

(b4) calculating an occupation ratio of said determined high-density region to said layout region;

(b5) executing said (b1) to (b4) steps again, if said calculated occupation ratio is equal to or more than 50%; and

(b6) determining said provisional interconnection layout as said interconnection layout, if said calculated occupation ratio is less than 50%.

12. The design program according to claim 10 , wherein said (C) step includes:

(c1) dividing said layout region into a plurality of strip regions, wherein a longitudinal direction of each of said plurality of strip regions is a first direction and said plurality of strip regions align in a second direction orthogonal to said first direction;

(c2) dividing said high-density region into said plurality of divided high-density regions such that a width of each of said plurality of divided high-density regions in said second direction is smaller than a width of said each strip region in said second direction; and

(c3) placing said plurality of divided high-density regions in respective strip regions among said plurality of strip regions.