Semiconductor apparatus having shield line provided between internal layer and input/output line in layout cell

1. A semiconductor apparatus, comprising:

an internal layer which connects together a plurality of transistor nodes that are formed in a layout cell;

a first power supply line which provides a predetermined voltage to the layout cell;

an input/output line which is connected to an input/output terminal of the plurality of transistors in the layout cell; and

a shield line placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line,

wherein the internal layer, the first power supply line, the shield line, and the first power supply line are provided in that order from a semiconductor substrate.

2. The semiconductor apparatus according to claim 1 , wherein

an end of the shield line in a first direction is placed in an outer part of the layout cell compared with an end which is the closest to a periphery of the layout cell along the second direction, the end selected from an end of the first power supply line and an end of the internal cell line, and

an end of the shield line in the second direction is placed in an outer part of the layout cell compared with an end of the internal cell line which is the closest to a periphery of the layout cell along the first direction.

3. The semiconductor apparatus according to claim 1 , wherein

an end of the shield line in a first direction is placed in an outer part of the layout cell compared with an end which is the closest to a periphery of the layout cell along a second direction, the end selected from an end of the first power supply line or an end of the internal cell line which is the closest to the periphery of the layout cell along the second direction and an end of the input/output line placed above the layout cell which is the closest to the periphery of the layout cell along the second direction, and

an end of the shield line in the second direction is placed in an outer part of the layout cell compared with an end of the internal cell line which is the closest to a periphery of the layout cell along the first direction.

4. The semiconductor apparatus according to claim I, wherein

an end of the input/output line placed above the layout cell which is the closest to a periphery of the layout cell along a second direction is placed in an inner part of the layout cell compared with an end which is the closest to a periphery of the layout cell along a first direction, the end selected from an end of the shield line in the first direction, an end of the first power supply line and an end of the internal cell line.

5. The semiconductor apparatus according to claim 2 , wherein

the first direction comprises a longitudinal direction of the first power supply line, and the second direction is substantially orthogonal to the first direction.

6. The semiconductor apparatus according to claim 3 , wherein

the first direction comprises a longitudinal direction of the first power supply line, and the second direction is substantially orthogonal to the first direction.

7. The semiconductor apparatus according to claim 4 , wherein

the first direction comprises a longitudinal direction of the first power supply line, and the second direction is substantially orthogonal to the first direction.

8. The semiconductor apparatus according to claim 1 , wherein

the layout cell further includes second power supply lines to provide a second power supply to transistors in the layout cell, and the internal cell line and the first power supply line arranged in parallel with the second power supply lines are placed in an area between the second power supply lines.

9. The semiconductor apparatus according to claim 1 , wherein

the layout cell includes at least one Static Random Access Memory (SRAM) cell.

10. The semiconductor apparatus according to claim 9 , wherein

the shield line comprises a electrode of a additional capacitor that is connected with a cross-coupling node of the SRAM cell and the first power supply line.

11. The semiconductor apparatus according to claim 1 , wherein

a plurality of layout cells are arranged adjacent to each other through a tap region where a global power supply line to provide a power supply to the plurality of layout cells is placed.

12. A semiconductor device, comprising:

a plurality of transistors formed in a layout cell;

an internal layer which is arranged in said layout cell to connect said transistor therebetween;

a first power supply line which is arranged in said layout cell to provide voltage to the transistors in the layout cell;

a conductive line which is arranged on said internal layer in said layout cell to provide voltage to the transistors; and

a shield line placed between the internal layer and the conductive line so as to cover the internal layer and first power supply line, said shield line projecting from an edge of the first power supply line,

wherein the internal layer, the first power supply line, the shield line, and the conductive line are provided in that order from a semiconductor substrate.

13. A semiconductor device, comprising:

a first layout cell;

a second layout cell provided adjacently to said first layout cell via a tap region;

wherein each of first and second layout cells comprises:

a plurality of transistors; and

a power supply line coupled to the plurality of transistors in the correspondingly one of the first to second layout cell,

a power source layer formed on the tap region to connect the power supply line in the first layout cell and the power supply line in the second layout cell; and

a shield line which covers the power supply line in the first and second layout cells and extends to the tap region to be provided under the power source layer to be connected to the power source layer.

14. The semiconductor device of claim 13 , further comprising:

a third layout cell provided adjacently to said second layout cell without the tap region intervening therebetween, coupled to the power supply line, and covered with the shield line.