Verification coverage extraction circuit and method, semiconductor device and emulation system
Disclosed is a verification coverage extraction circuit for extracting the verification coverage rate at the time of circuit verification employing an emulation device, in which a state of the current cycle and a state of the next cycle of a state machine are coupled by a data coupling circuit into an item of data, this data is compressed to a data width which is a necessary minimum to express state transition by an encoder circuit, the state transition information is stored in a memory, with an output of the encoder circuit as an address, and the verification coverage information at the time of functional verification of a circuit under verification is extracted from the memory.
1 . A verification coverage extraction circuit for extracting verification coverage information of a circuit under verification, comprising:
a memory; and
a circuit unit that receives a state value of a current cycle of a state machine of said circuit under verification, and a state value of a next cycle thereof, at the time of functional verification of said circuit under verification and that writes a preset logic value in said memory, with paired bit data of said state value of the current cycle and said state value of the next cycle of said state machine or data derived from said bit data as address information; wherein in said memory state transition information of said circuit under verification is retained.
2 . The verification coverage extraction circuit according to claim 1 , wherein said circuit unit comprises:
a data coupling circuit that concatenates paired bit data of said state value of the current cycle and said state value of the next cycle of said state machine; and
an encoder circuit that receives the concatenated data from said data coupling circuit, and compresses the concatenated data to data of a necessary minimum bit width to express the information of state transitions allowed in accordance with operational design parameters of said circuit under verification, said encoder circuit outputting the resulting compressed data to said memory as the address information.
3 . The verification coverage extraction circuit according to claim 1 , wherein said circuit under verification and said verification coverage extraction circuit compose an emulation device.
4 . A semiconductor device having a verification coverage extraction circuit set forth in claim 1 .
5 . The verification coverage extraction circuit according to claim 2 , wherein said data coupling circuit receives state values of the current cycle and the next cycle of the state machine of said circuit under verification, arranged within an electrically reprogrammable semiconductor device mounted on an evaluation substrate, concatenates the state values of the current and next cycles of said state machine and outputs resulting concatenated data; and
said memory retains a first logic value with said encoded data output from said encoder circuit as an address.
6 . The verification coverage extraction circuit according to claim 5 , wherein said circuit under verification includes a control unit and a data path unit that receives a control signal from said control unit;
said control unit including said state machine;
said circuit under verification outputting the states of the current cycle and the next cycle of said state machine.
7 . The verification coverage extraction circuit according to claim 5 , wherein said data coupling circuit includes a combination circuit that couples the states of the current cycle and the next cycle retained within said state machine to output concatenated cycle states as a data representation.
8 . The verification coverage extraction circuit according to claim 5 , wherein said memory receives data output from said encoder circuit as an address and also receives a signal of a level corresponding to a first logic value as write data;
said memory is driven linked with said circuit under verification; and
said memory receives a write enable signal from a host computer which is connected to an emulation device including said verification coverage extraction circuit;
read data from said memory being transferred to said host computer.
9 . The verification coverage extraction circuit according to claim 5 , wherein a second logic value is written in said memory at the time of resetting.
10 . An emulation system comprising:
an emulation device having mounted a circuit under verification and a verification coverage extraction circuit set forth in claim 5 , on a reprogrammable semiconductor device, and
a host computer connected to said emulation device.
11 . A method for extracting verification coverage of a circuit under verification, said method comprising:
receiving a state value of a current cycle of a state machine of said circuit under verification, and a state value of a next cycle thereof, at the time of functional verification of said circuit under verification; and
writing a preset logic. value in a memory, with paired bit data of said state of the current cycle and said state of the next cycle of said state machine or with data derived from said bit data as the address information; the state transition information of said circuit under verification being retained in said memory.
12 . The method according to claim 11 , comprising:
concatenating a set of a state value of a current cycle of a state machine of said circuit under verification and a state value of a next cycle thereof to an item of data; and
writing a first logic value in a memory, with said data obtained by concatenation or with a data obtained on reducing the number of bits of said data by compression, as address information.