Variable capacitor array

1 . A digitizer comprising:

a digitizer sensor comprising at least one pair of conductive lines coupled to at least one differential amplifier through which a difference signal is detected; and

at least one capacitor operative to balance differences in parasitic capacitance between the conductive lines of the at least one pair of conductive lines.

2 . The digitizer according to claim 1 wherein the at least one capacitor is coupled to at least one conductive line of the pair.

3 . The digitizer according to claim 1 wherein a capacitor is coupled to each conductive line of the pair.

4 . The digitizer according to claim 1 wherein a capacitor is coupled to at least one conductive line through a switch.

5 . The digitizer according to claim 4 wherein the switch is a MOSFET switch.

6 . The digitizer according to claim 1 wherein the at least one capacitor is a variable capacitor.

7 . The digitizer according to claim 1 wherein the at least one capacitor has a capacitance level between 0-3.2 pF.

8 . The digitizer according to claim 1 wherein the at least one capacitor includes a group of capacitors, each capacitor in the group associated with a switch.

9 . The digitizer according to claim 1 wherein the at least one capacitor includes a group of capacitors connected in parallel, each capacitor in the group associated with a switch.

10 . The digitizer according to claim 8 wherein capacitors in the group of capacitors have a capacitance value double that of one other capacitor in the group.

11 . The digitizer according to claim 8 wherein the switch is a MOSFET switch.

12 . The digitizer according to claim 1 comprising a fixed capacitor coupled to at least one conductive line of the pair.

13 . The digitizer according to claim 1 wherein the at least one pair of conductive lines are parallel to each other.

14 . The digitizer according to claim 1 wherein the at least one pair of conductive lines are distanced by at least the effective range of a user input signal.

15 . The digitizer according to claim 1 comprising multiple pairs of conductive lines arranged in a matrix of vertical and horizontal conductive lines.

16 . The digitizer according to claim 1 wherein an object placed over one of the conductive lines of the pair produces an output on a differential amplifier.

17 . The digitizer according to claim 1 comprising circuitry operative to adjust the capacitance level of the at least one capacitor.

18 . The digitizer according to claim 17 wherein the at least one capacitor has a capacitance operative to increase the common mode rejection ratio of the at least one differential amplifier.

19 . The digitizer according to claim 1 comprising circuitry operative to detect and sample the difference signal.

20 . The digitizer according to claim 1 comprising circuitry operative to filter the difference signal.

21 . The digitizer according to claim 1 wherein the capacitor has a capacitance operative to decrease a steady-state noise in the difference signal.

22 . The digitizer according to claim 1 comprising one or more ASICs wherein the one or more ASICs comprises:

the at least one capacitor;

the at least one differential amplifier.

23 . The digitizer according to claim 22 wherein the ASIC is operative to adjust the capacitance level of the at least one capacitor.

24 . The digitizer according to claim 22 wherein the ASIC is operative to receive capacitance level from a digital unit.

25 . A method for reducing the effects of unbalanced parasitic capacitance in a digitizer comprising:

detecting a difference signal between a pair of conductive lines of a digitizer sensor; and

coupling a capacitor to at least one conductive line of the pair of conductive lines to reduce the imbalance.

26 . The method according to claim 25 wherein the difference signal is detected while no object is placed over the digitizer sensor.

27 . The method according to claim 25 wherein the difference signal is obtained from unbalanced capacitance on the pair of conductive lines.

28 . The method according to claim 25 wherein the difference signal is obtained from unbalanced circuitry of the digitizer.

29 . The method according to claim 25 wherein the capacitor is coupled to each conductive line of the pair.

30 . The method according to claim 25 wherein the capacitor is coupled to the at least one conductive line through a switch.

31 . The method according to claim 30 wherein the switch is a MOSFET switch.

32 . The method according to claim 25 wherein the capacitor is a variable capacitor.

33 . The method according to claim 25 wherein the capacitor has a capacitance level between 0-3.2 pF.

34 . The method according to claim 25 wherein the capacitor includes a group of capacitors, each capacitor in the group associated with a switch.

35 . The method according to claim 25 wherein the capacitor includes a group of capacitors connected in parallel, each capacitor in the group associated with a switch.

36 . The method according to claim 34 wherein the switch is a MOSFET switch.

37 . The method according to claim 34 comprising controlling the switch to obtain a desired capacitance level.

38 . The method according to claim 25 comprising coupling a fixed capacitor to at least one conductive line of the pair.

39 . The method according to claim 25 comprising inducing an AC signal onto the pair of conductive lines.

40 . The method according to claim 25 comprising adjusting the capacitance level to a value that corresponds to difference signal below a defined threshold.

41 . The method according to claim 25 comprising:

detecting the difference signals for a range of capacitance levels coupled on the at least one conductive line; and

selecting a capacitance level from the range of capacitance levels that yields a minimum difference signal.

42 . The method according to claim 25 wherein the capacitor is integrated into an ASIC.

43 . The method according to claim 42 wherein the ASIC is operative to adjust the capacitance level of the capacitor.

44 . The method according to claim 25 wherein a differential amplifier is operative to detect the difference signal.

45 . The method according to claim 44 wherein the capacitor has a capacitance operative to increase the common mode rejection ratio of the differential amplifier.

46 . The method according to claim 25 comprising filtering and sampling the difference signal.

47 . A method of operating a sensor comprising at least one array of conductive lines spaced apart in a given direction and a plurality of differential amplifiers to which said conductive lines are pairwise coupled, the method including:

adding a capacitance to at least one line of each pair operative to compensate for imbalance capacitance;

electrifying each line of a given pair with a same voltage; and

determining whether a touch occurs near a conductor from an output voltage of said amplifier.

48 . The method according to claim 47 wherein the imbalanced is operative to balance differences in parasitic capacitance between the conductive lines of the pairs.

49 . The method according to claim 47 wherein the capacitance are selected using the method according to claim 25 .

50 . The method according to claim 47 comprising a second array of conductive lines spaced apart in a given direction, the second array perpendicular to the given array.

51 . The method according to claim 47 wherein the pairwise coupled conductive lines are parallel lines.

52 . The method according to claim 47 wherein the pairwise coupled conductive lines are spaced apart at a distance greater than the width of a finger.

53 . A digitizer comprising:

a digitizer sensor comprising at least one pair of conductive lines coupled to at least one differential amplifier through which a difference signal is detected; and

at least one capacitor operative to minimize the output signal of the differential amplifier when no object is present over the digitizer sensor.