Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps
View Patent ↗In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.
1. A semiconductor device comprising:
a semiconductor body with a trench;
a gate silicon dioxide layer formed within the trench of said semiconductor body;
a first gate electrode formed on a sidewall of the trench of said semiconductor body via said gate silicon dioxide layer;
an insulating layer formed on a bottom of the trench of said semiconductor body via said gate silicon dioxide layer and surrounded by said first gate electrode, said insulating layer excluding silicon dioxide and having different etching characteristics from those of silicon dioxide; and
a second gate electrode buried in the trench of said semiconductor body, said second gate electrode being in contact with said first gate electrode and said insulating layer.
2. The semiconductor device as set forth in claim 1 , wherein said semiconductor body comprises:
a semiconductor substrate;
an epitaxial semiconductor layer grown on said semiconductor substrate, said epitaxial semiconductor layer having the trench of said semiconductor body.
3. The semiconductor device as set forth in claim 1 , wherein said semiconductor body comprises a semiconductor substrate having impurity diffusion regions,
the trench of said semiconductor body being formed within said impurity diffusion regions.
4. The semiconductor device as set forth in claim 1 , wherein said insulating layer comprises one of a silicon nitride layer and a silicon oxynitride layer.
5. The semiconductor device as set forth in claim 1 , wherein said first gate electrode comprises a polycrystalline silicon layer, and said second gate electrode layer comprises one of a polycrystalline silicon layer and a refractory metal layer.