Programmable microcontroller architecture(mixed analog/digital)
View Patent ↗A microcontroller with analog/digital Programmable System On-a-Chip (PSoC) architecture including multiple digital PSoC blocks and multiple analog PSoC blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The PSoC architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The PSoC array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the PSoC blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.
1. A circuit comprising:
a plurality of circuit blocks, wherein at least one of the circuit blocks is an analog circuit block and at least one of the circuit blocks is a digital circuit block;
a bus coupling analog input/output data and digital input/output data for the plurality circuit blocks; and
a clock controlling the coupling of the analog input/output data and the digital input output data to the bus.
2. A circuit according to claim 1 further comprising:
a programmable interconnect structure coupled to the plurality of circuit blocks.
3. A circuit according to claim 2 wherein the programmable interconnect structure is configured to dynamically reconfigure the plurality of circuit blocks to implement one of a plurality of functions.
4. A circuit according to claim 1 wherein the circuit comprises a single integrated circuit semiconductor chip.
5. A circuit according to claim 1 wherein the at least one analog circuit block comprises a continuous time analog circuit.
6. A circuit according to claim 1 wherein the at least one analog circuit block comprises a switched capacitor analog circuit.
7. A microcontroller comprising:
a plurality of programmable analog circuit blocks;
a plurality of programmable digital circuit blocks;
a programmable interconnect coupling the analog circuit blocks and the digital circuit blocks; and
a bus coupling analog input/output data and digital input/output data for the analog circuit blocks and the digital circuit block.
8. A microcontroller according to claim 7 wherein one of the digital circuit blocks is configured to implement logical operations.
9. A microcontroller according to claim 7 wherein one of the digital circuit blocks is configured to implement computational operations.
10. A microcontroller according to claim 7 wherein the programmable interconnect structure and the programmable analog circuit blocks and the plurality of programmable digital circuit blocks are constructed on a semiconductor chip.
11. A microcontroller according to claim 7 wherein the programmable analog circuit blocks comprise at least one continuous time analog circuit block.
12. A microcontroller according to claim 7 wherein the programmable analog circuit blocks comprise at least one switched capacitor analog circuit block.
13. A microcontroller according to claim 7 wherein the programmable digital circuit blocks comprise at least one digital multi-function circuit block having a first set of digital functions and at least one digital multi-function circuit block having a second set of digital functions different from the first set.
14. A method of providing a dynamically programmable analog/digital communication interface circuit, comprising:
configuring a plurality of programmable analog circuit blocks to implement at least one of a plurality of analog functions,
configuring a plurality of programmable digital circuit blocks to implement at least one of a plurality of digital functions; and
configuring a routing matrix to couple analog data and digital data between the programmable analog circuit blocks and the programmable digital circuit blocks.
15. The method according to claim 14 wherein flash memory is used to program the routing matrix and the plurality of programmable analog circuit blocks and the plurality of programmable digital circuit blocks and to enable dynamic circuit reconfiguration.
16. The method according to claim 14 wherein the programmable analog circuit blocks comprise at least one continuous time analog circuit and at least one switched capacitor analog circuit.
17. The method according to claim 14 wherein the programmable digital circuit blocks comprise at least one standard digital multi-function circuit having a first set of digital functions and at least one enhanced digital multi-function circuit having at least one function differing from the first set of digital functions.
18. The method according to claim 14 wherein the programmable analog circuit blocks comprise at least one multi-function circuit programmable for at least one of the plurality of analog functions and at least one fixed function circuit programmable for a fixed function with at least one of a number of different parameters.
19. The method according to claim 14 wherein the plurality of digital functions comprises logical operations.
20. The method according to claim 14 wherein the plurality of digital functions comprises computational operations.