Accelerated deserialized boot implementation for a multiprocessor system
View Patent ↗An accelerated boot process for a multiprocessor system and system components for use with the process are disclosed. Each processor caches at least one compressed system image in local nonvolatile memory. The processors boot concurrently, each using a local image. After a master processor is booted, the other processors verify with the master that each has booted a correct image version. Various redundancy and fallback features are described, which guarantee that all cards can boot and operate even if the preferred local system image contains a defect.
1. A method of booting a system comprising multiple cooperating processors, the method comprising:
concurrently executing on each of a first plurality of the processors, not all sharing a common local memory system, a boot image for that processor stored in nonvolatile memory local to that processor;
during execution of the boot image on each of the first plurality of the processors, selecting a system image for each processor stored in nonvolatile memory local to that processor;
on each of the first plurality of the processors, booting into the selected system image for each processor; and
on each of the first plurality of the processors, communicating with one of the multiple cooperating processors serving as a master boot processor for that processor to validate that the selected system image for that processor is the correct system image.
2. The method of claim 1 , wherein the system images stored in nonvolatile memory local to the processors are stored in a compressed format, the method further comprising each processor in the first plurality decompressing the selected system image to an uncompressed format in memory local to that processor prior to booting into that system image.
3. The method of claim 2 , further comprising each processor in the first plurality validating its selected compressed system image.
4. The method of claim 3 , wherein validating comprises a processor checking a persistent system image valid flag stored in nonvolatile memory local to that processor.
5. The method of claim 4 , wherein validating comprises a processor checking a signature stored with its selected system image, and marking the system image valid flag invalid if the signature check fails.
6. The method of claim 4 , wherein validating comprises a processor performing a checksum operation for its selected system image, and marking the system image valid flag invalid if the checksum operation fails.
7. The method of claim 4 , wherein validating comprises a processor checking the success of its system image decompression operation, and marking the system image valid flag invalid if the decompression operation fails.
8. The method of claim 3 , further comprising, if validation fails on one of the first plurality of processors for a selected system image, selecting an alternate system image stored in nonvolatile memory local to that processor, setting a persistent system image selection flag stored in nonvolatile memory local to that processor to indicate the identity of the alternate system image, and attempting to reboot into the alternate system image.
9. The method of claim 8 , wherein, if no local system image can be successfully booted by one of the first plurality of processors, the processor reverts to a boot mode that requests a system image from the master boot processor.
10. The method of claim 8 , further comprising maintaining, for each of the first plurality of processors, a system image boot count in nonvolatile memory local to that processor, each such processor attempting to boot an alternate system image after the boot count reaches a retry threshold.
11. The method of claim 10 , wherein a processor continues to increment the boot count with each boot retry after switching to the alternate system image, the processor reverting to a boot mode that requests a system image from the master boot processor after the boot count reaches an expedite threshold.
12. The method of claim 1 , wherein when the check with the master boot processor indicates that an incorrect system image version was booted, the processor checks its local system images to determine if it has a valid correct version of the system image indicated by the master boot processor, the processor rebooting into that valid correct version if it exists among the local system images.
13. The method of claim 12 , wherein if the processor determines that it does not have the valid correct version of the system image stored locally, it requests the system image from the master boot processor.
14. The method of claim 1 , further comprising each processor storing persistent control data in a nonvolatile memory local to that processor, the persistent control data used to save state information for the boot process.
15. The method of claim 14 , wherein the persistent control data is stored in a nonvolatile memory separate from the nonvolatile memory storing the system images.
16. The method of claim 14 , wherein the persistent control data comprises state information on the boot path used in the current boot process.
17. The method of claim 16 , wherein a processor allows update of a system image stored in nonvolatile memory local to that processor unless the stored system image corresponds to the system image currently executing on the processor.
18. The method of claim 1 , wherein the first plurality of the processors comprises all of the multiple cooperating processors.
19. The method of claim 1 , wherein at least two of the first plurality of processors share common local nonvolatile memory, each processor storing at least one system image in the shared local nonvolatile memory, the at least one system image selectable during execution of the boot image for that processor.
20. The method of claim 19 , wherein the at least two of the processors share some components of their stored system images in the shared local nonvolatile memory.
21. The method of claim 19 , further comprising a bus agent translating requests from the at least two of the first plurality of processors to point to areas of the shared local nonvolatile memory designated for each processor.