IP Library Granted Patent US 7,379,044
Granted Patent B2
US 7,379,044 · App. 11/802,296 · Granted May 27, 2008

Image display apparatus

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Quick Facts
Patent No.
US 7,379,044
App. No.
11/802,296
Granted
May 27, 2008
Kind
B2
Abstract

An image display apparatus includes pixels each having a light emitting element and a pixel circuit, analog signal lines and current-supply lines. The pixel circuit includes first and second TFTs and first and second capacitors. Drain and source electrodes of the first TFT are coupled to the light emitting element and one of the current-supply lines, respectively, and drain and source electrodes of the second TFT are coupled to a gate electrode of the first TET and one of wiring lines within the pixel circuit, respectively. Two electrodes of the first capacitor are coupled to the gate electrode of the first TFT and one of the wiring lines within the pixel circuit, respectively. Two electrodes of the second capacitor are coupled to a gate electrode of the second TFT and a line supplied with a triangular waveform voltage, respectively.

Claims (23)

1. An image display apparatus comprising:

a plurality of pixels arranged in a matrix fashion on a substrate, each of said plurality of pixels being provided with a light emitting element with light intensity thereof varying with a current therethrough and a pixel circuit which drives said light emitting element;

a plurality of analog signal lines disposed on said substrate which input an analog display voltage signal into each of said plurality of pixels; and

a plurality of current-supply lines which supply a current to said light emitting element provided in each of said plurality of pixels.

wherein:

said pixel circuit provided in each of said plurality of pixels includes a first thin film transistor, a second thin film transistor, a first capacitor and a second capacitor;

a drain electrode and a source electrode of said first thin film transistor are coupled to said light emitting element and a corresponding one of said plurality of current-supply lines, respectively;

a drain electrode and a source electrode of said second thin film transistor are coupled to a gate electrode of said first thin film transistor and one of wiring lines disposed within said pixel circuit, respectively;

one electrode of said first capacitor is coupled to said gate electrode of said first thin film transistor, and another electrode of said first capacitor is coupled to one of said wiring lines disposed within said pixel circuit;

one electrode of said second capacitor is coupled to a gate electrode of said second thin film transistor, and another electrode of said second capacitor is coupled to a line supplied with a triangular waveform voltage during a specified portion of a frame period, said triangular waveform voltage increasing or decreasing at a uniform rate.

2. The image display apparatus according to claim 1 , wherein:

said one electrode of said second capacitor is coupled to said gate electrode of said second thin film transistor, and said another electrode of said second capacitor is coupled to a corresponding one of said plurality of analog signal lines; and

said gate electrode of said second thin film transistor is supplied with said triangular waveform voltage via said second capacitor and said corresponding one of said plurality of analog signal lines during a specified portion of a frame period, said triangular waveform voltage increasing or decreasing at a uniform rate.

3. The image display apparatus according to claim 1 , further comprising a plurality of control lines each of which supplies a digital control signal to said pixel circuit in a corresponding one of said plurality of pixels, wherein said drain electrode and said source electrode of said second thin film transistor are coupled to said gate electrode of said first thin film transistor and a corresponding one of said plurality of control lines, respectively.

4. The image display apparatus according to claim 1 , further comprising a common electrode common to said plurality of pixels, wherein said drain electrode and said source electrode of said second thin film transistor are coupled to said gate electrode of said first thin film transistor and said common electrode, respectively.

5. The image display apparatus according to claim 1 , wherein said one electrode of said first capacitor is coupled to said gate electrode of said first thin film transistor, and said another electrode of said first capacitor is coupled to a corresponding one of said plurality of current-supply lines.

6. The image display apparatus according to claim 1 , further comprising a common electrode common to said plurality of pixels, wherein said one electrode of said first capacitor is coupled to said gate electrode of said first thin film transistor, and said another electrode of said first capacitor is coupled to said common electrode.

7. The image display apparatus according to claim 1 , wherein said pixel circuit further comprises a third thin film transistor, and a drain electrode and a source electrode of said third thin film transistor are coupled to said gate electrode and said drain electrode of said second thin film transistor, respectively.

8. The image display apparatus according to claim 7 , further comprising a plurality of control lines each of which supplies a digital control signal to said pixel circuit in a corresponding one of said plurality of pixels, wherein said gate electrode of said third thin film transistor is coupled to a corresponding one of said plurality of control lines.

9. The image display apparatus according to claim 1 , further comprising a plurality of control lines each of which supplies a digital control signal to said pixel circuit in a corresponding one of said plurality of pixels, wherein said pixel circuit further comprises a fourth thin film transistor, and a source electrode of said fourth thin film transistor is coupled to said one electrode of said first capacitor, and a drain electrode of said fourth thin film transistor is coupled to a corresponding one of said plurality of control lines.

10. The image display apparatus according to claim 1 , wherein said pixel circuit further comprises a fifth thin film transistor coupled in series with said first thin film transistor.

11. The image display apparatus according to claim 1 , further comprising a power supply which supplies an electric current to said plurality of current-supply lines and a switch provided between said plurality of current-supply lines and said switch, wherein said switch is configured such that said switch is turned ON when said pixel circuit is supplied with said triangular waveform voltage.

12. The image display apparatus according to claim 1 , wherein all of said thin film transistors fabricated on said substrate are of only one n-channel and p-channel types.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2018
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.; JAPAN DISPLAY INC.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 046988/0801 →
COMPANY SPLIT PLAN TRANSFERRING FIFTY (50) PERCENT SHARE OF PATENTS AND PATENT APPLICATIONS Recorded Dec 12, 2011
From: HITACHI DISPLAYS, LTD.
To: IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027362/0466 →
COMPANY SPLIT PLAN TRANSFERRING ONE HUNDRED (100) PERCENT SHARE OF PATENT AND PATENT APPLICATIONS Recorded Dec 12, 2011
From: HITACHI, LTD.
To: HITACHI DISPLAYS, LTD.
Reel/Frame 027362/0612 →
MERGER/CHANGE OF NAME Recorded Dec 12, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027363/0315 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2010
From: HITACHI, LTD.
To: HITACHI DISPLAYS, LTD.
Reel/Frame 025008/0380 →