Data transfer system and data processing apparatus

1 . A data transfer system, comprising:

a data transmitting section which transmits a second clock signal generated by frequency dividing a first clock signal, and a data signal including two bits for each cycle of said second clock signal; and

a data receiving section which receives said second clock signal and said data signal, and which independently detects the two bits included in said data signal for each cycle of said second clock signal.

2 . The data transfer system according to claim 1 , wherein

a clock frequency of said second clock signal is a half of a clock frequency of said first clock signal, and

in said data signal transmitted from said data transmitting section, one bit is assigned to each of a HIGH period and a LOW period in one cycle of said second clock signal.

3 . The data transfer system according to claim 2 , wherein

said data receiving section includes:

a first system which detects one bit assigned to the HIGH period included in said data signal, for each cycle of said second clock signal; and

a second system which detects one bit assigned to the LOW period included in said data signal for each cycle of said second clock signal.

4 . The data transfer system according to claim 3 , wherein

said first system includes:

a latching portion which latches said data signal in the HIGH period of said second clock signal;

a first sampling portion which samples said data signal latched by said latching portion, at a timing of said second clock signal; and

a first data detecting portion which detects data obtained by said first sampling portion, for each cycle of said second clock signal, and

said second system includes:

a second sampling portion which samples said data signal at the timing of said second clock signal; and

a second data detecting portion which detects data obtained by said second sampling portion, for each cycle of said second clock signal.

5 . The data transfer system according to claim 1 , wherein

said data signal is in a serial format.

6 . The data transfer system according to claim 1 , wherein

said data signal is in a parallel format, and includes two sets of data of a data width number of said data signal, for each cycle of said second clock signal, and

said data receiving section independently detects said two sets of data included in said data signal, for each cycle of said second clock signal.

7 . A data processing apparatus wherein said apparatus transmits a second clock signal generated by frequency dividing a first clock signal, and a data signal including two bits for each cycle of said second clock signal.

8 . The data processing apparatus according to claim 7 , wherein

a clock frequency of said second clock signal is a half of a clock frequency of said first clock signal, and

in said data signal transmitted from said data transmitting section, one bit is assigned to each of a HIGH period and a LOW period in one cycle of said second clock signal.

9 . The data processing apparatus according to claim 7 , wherein

said data signal is in a serial format.

10 . The data processing apparatus according to claim 7 , wherein

said data signal is in a parallel format, and includes two sets of data of a data width number of said data signal, for each cycle of said second clock signal, and

said apparatus independently detects said two sets of data included in said data signal, for each cycle of said second clock signal.

11 . A data processing apparatus wherein said apparatus receives a clock signal and a data signal including two bits for each cycle of said clock signal, and independently detects the two bits included in said data signal, for each cycle of said clock signal.

12 . The data processing apparatus according to claim 11 , wherein said apparatus comprises:

a first system which detects one bit assigned to the HIGH period included in said data signal, for each cycle of said clock signal; and

a second system which detects one bit assigned to the LOW period included in said data signal, for each cycle of said clock signal.

13 . The data processing apparatus according to claim 12 , wherein

said first system includes:

a latching portion which latches said data signal in the HIGH period of said clock signal;

a first sampling portion which samples said data signal latched by said latching portion, at a timing of said clock signal; and

a first data detecting portion which detects data obtained by said first sampling portion, for each cycle of said clock signal, and

said second system includes:

a second sampling portion which samples said data signal at the timing of said clock signal; and

a second data detecting portion which detects data obtained by said second sampling portion, for each cycle of said clock signal.

14 . The data processing apparatus according to claim 11 , wherein

said data signal is in a serial format.

15 . The data processing apparatus according to claim 11 , wherein

said data signal is in a parallel format, and includes two sets of data of a data width number of said data signal, for each cycle of said clock signal, and

said apparatus independently detects said two sets of data included in said data signal, for each cycle of said clock signal.

16 . A data processing apparatus comprising:

a clock frequency dividing section which frequency divides a first clock signal to generate a second clock signal having a clock frequency that is a half of a clock frequency of said first clock signal;

a high-speed processing section which outputs a data signal including two bits for each cycle of said second clock signal, based on said first clock signal; and

a low-speed processing section which receives said second clock signal and said data signal, and which independently detects the two bits included in said data signal, for each cycle of said second clock signal.

17 . The data processing apparatus according to claim 16 , wherein

in said data signal output from said high-speed processing section, one bit is assigned to each of a HIGH period and a LOW period in one cycle of said second clock signal.

18 . The data processing apparatus according to claim 17 , wherein

said low-speed processing section includes:

a first system which detects one bit assigned to the HIGH period included in said data signal, for each cycle of said second clock signal; and

a second system which detects one bit assigned to the LOW period included in said data signal, for each cycle of said second clock signal.

19 . The data processing apparatus according to claim 18 , wherein

said first system includes:

a latching portion which latches said data signal in the HIGH period of said second clock signal;

a first sampling portion which samples said data signal latched by said latching portion, at a timing of said second clock signal; and

a first data detecting portion which detects data obtained by said first sampling portion, for each cycle of said second clock signal, and

said second system includes:

a second sampling portion which samples said data signal at the timing of said second clock signal; and

a second data detecting portion which detects data obtained by said second sampling portion, for each cycle of said second clock signal.

20 . The data processing apparatus according to claim 16 , wherein

said data signal is in a serial format.

21 . The data processing apparatus according to claim 16 , wherein

said data signal is in a parallel format, and includes two sets of data of a data width number of said data signal, for each cycle of said second clock signal, and

said low-speed processing section independently detects said two sets of data included in said data signal, for each cycle of said second clock signal.