Multilayered bus system
The present invention provides a multilayered bus system capable of performing transition to a power-saving mode reliably and rapidly. When a mode designation signal for designating the power-saving mode is outputted from a clock controller in response to mode setting information outputted from a CPU, respective arbiters respectively output response signals for prohibiting access to bus slaves to their corresponding bus masters. When the power-saving mode is designated by the mode designation signal, the response signal for prohibiting access is outputted from the arbiter, and an end signal indicating that the respective bus slaves do not perform data transfers for a predetermined period of time is outputted from a monitor, a control signal for stopping the supply of a system clock is outputted from the clock controller to a clock generator.
1 . A multilayered bus system which connects between a plurality of bus masters each including a central processing unit and a plurality of bus slaves using a plurality of common buses and performs data transfers in sync with a system clock through a plurality of buffer memories for temporarily holding data therein, said multilayered bus system comprising:
a register which holds therein mode setting information for designating a power-saving mode or a normal operation mode supplied from said each central processing unit and outputs a mode setting signal therefrom;
arbiters each of which outputs a response signal for prohibiting access to each of the bus slaves to each of the bus masters when the power-saving mode is designated by the mode setting signal;
a monitor which monitors the presence or absence of a data transfer between each of the bus slaves and each of the buffer memories when the power-saving mode is designated by the mode setting signal, and outputs an end signal when the data transfer is not being performed over a predetermined period of time; and
a clock controller which outputs a control signal for stopping the supply of the system clock when the power-saving mode is designated by the mode setting signal, the response signal is outputted from each of the arbiters and the end signal is outputted from the monitor.
2 . A multilayered bus system which connects between a plurality of bus masters each including a central processing unit and a plurality of bus slaves using a plurality of common buses and performs data transfers in sync with a system clock through buffer memories for temporarily holding data therein, said multilayered bus system comprising:
a register which holds therein mode setting information for designating a power-saving mode or a normal operation mode supplied from said each central processing unit and outputs a mode setting signal therefrom;
arbiters each of which outputs a response signal for prohibiting access to each of the bus slaves to each of the bus masters when the power-saving mode is designated by the mode setting signal;
a monitor which monitors whether transfer data is being held in each of the buffer memories when the power-saving mode is designated by the mode setting signal and outputs an end signal when data are found not to exist in all of the buffer memories; and
a clock controller which outputs a control signal for stopping the supply of the system clock when the power-saving mode is designated by the mode setting signal, the response signal is outputted from each of the arbiters and the end signal is outputted from the monitor.