IP Library Granted Patent US 7,723,221
Granted Patent B2
US 7,723,221 · App. 11/803,242 · Granted May 25, 2010

Stacked film patterning method and gate electrode forming method

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Quick Facts
Patent No.
US 7,723,221
App. No.
11/803,242
Granted
May 25, 2010
Kind
B2
Abstract

A stacked film patterning method is provided which is capable of reliably removing residual substances remaining after etching of a metal film, improving etching uniformity of a silicon film, and preventing an occurrence of etching residues. A micro-crystal film and a chromium film are sequentially formed on an insulating film serving as a front-end film and the chromium film is etched to be patterned by using a resist as a mask. Next, a micro-crystal silicon film on which the residual substances exist is exposed to plasma of a mixed gas including chlorine gas and oxygen gas to selectively etch the residual substances on a surface of the micro-crystal silicon film. After that, the micro-crystal silicon film is dry etched.

Claims (13)

1. A stacked film patterning method for obtaining a desired stacked film pattern by etching a stacked film comprising a lower layer film made of a conductive semiconductor and an upper layer film made of metal, said method comprising:

a first etching process of removing a specified region of said upper layer film made of said metal by using a wet-etching method;

a second etching process, following said first etching process, of removing residues of said metal not removed by said first etching process or a compound of said metal with said conductive semiconductor by using plasma of a mixed gas comprising chlorine gas and oxygen gas after completion of said first etching process; and

a third etching process, following said second etching process, of removing said lower layer film made of said conductive semiconductor by using a dry-etching method after completion of said second etching process, wherein said conductive semiconductor is selected from the group consisting of micro-crystal silicon, polycrystalline silicon, amorphous silicon, and germanium polycrystalline silicon.

2. The stacked film patterning method according to claim 1 , wherein said lower layer film is made of polycrystalline silicon or micro-crystal silicon and said upper layer film is made of metal selected from a group consisting of chromium, molybdenum, tungsten, and tantalum or of an alloy comprising said metal.

3. The stacked film patterning method according to claim 1 , wherein a ratio of a flow rate of said oxygen gas to said chlorine gas is set to be within a range between 30% and 300%.

4. The stacked film patterning method according to claim 3 , wherein said ratio of said flow rate is set to be within a range between 50% and 200%.

5. The stacked film patterning method according to claim 1 , wherein said upper layer film is made of chromium, and ammonium cerium nitrate etching solution is used in said wet-etching method.

6. A gate electrode forming method for obtaining a desired gate electrode pattern by forming a stacked film comprising a lower layer film made of a conductive semiconductor and an upper layer film made of metal on a semiconductor film and gate insulating film deposited sequentially on a substrate and by etching said stacked film, said method comprising:

a first etching process of removing a specified region of said upper layer film made of said metal by using a wet-etching method;

a second etching process, following said first etching process, of removing residues of said metal or a compound of said metal not removed by said first etching process with said conductive semiconductor by using plasma of a mixed gas comprising chlorine gas and oxygen gas after completion of said first etching process; and

a third etching process, following said second etching process, of removing said lower layer film made of said conductive semiconductor by using a dry-etching method after completion of said second etching process, wherein said conductive semiconductor is selected from the group consisting of micro-crystal silicon, polycrystalline silicon, amorphous silicon and germanium polycrystalline silicon.

7. The gate electrode forming method according to claim 6 , wherein said upper layer film is made of chromium, and an ammonium cerium nitrate etching solution is used in said wet-etching method.

Assignments (3)
CHANGE OF NAME Recorded Nov 8, 2011
From: NEC LCD TECHNOLOGIES, LTD.
To: NLT TECHNOLOGIES, LTD.
Reel/Frame 027189/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2010
From: NEC CORPORATION
To: NEC LCD TECHNOLOGIES, LTD.
Reel/Frame 024495/0216 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2007
From: HAYASHI, KENICHI
To: NEC CORPORATION; NEC LCD TECHNOLOGIES, LTD.
Reel/Frame 019327/0320 →