Analog/digital broadcast signal receiver
A comparator for comparing an AFC output an analog demodulation circuit with a predetermined reference voltage Vref, an OR gate to which two inputs including an output of the comparator and a channel select signal are input, and a switch for connecting a crystal oscillator of a digital demodulation circuit to the digital demodulation circuit when an output of the OR gate is “H (or 1)” are provided. When an analog broadcast signal that should be received is not normally received, the crystal oscillator of the digital demodulation circuit is connected to the digital demodulation circuit to operate the digital demodulation circuit. Then, the channel select signal is supplied to a PLL circuit of a tuner front end via the digital demodulation circuit.
1 . A broadcast signal receiver, comprising:
a frequency conversion circuit for receiving broadcast signals in which an analog broadcast signal and a digital broadcast signal are mixed and for performing a frequency conversion into one of an analog intermediate frequency and a digital intermediate frequency whose frequency is set in accordance with a control signal that is supplied to a built-in PLL circuit;
an analog signal demodulation circuit for demodulating the analog broadcast signal of the analog broadcast signal output from the frequency conversion circuit;
a digital demodulation circuit having a signal transmission line that supplies the control signal to the PLL circuit passing therein and is connected to the PLL circuit, for attenuating noise on the signal transmission line and for demodulating the digital broadcast signal of the digital intermediate frequency output from the frequency conversion circuit;
a clock signal generation circuit for generating a clock signal that causes the digital demodulation circuit to operate; and
a control circuit for stopping supply of the clock signal with use of a signal from an outside at a time of reception of the analog broadcast, for determining whether or not the analog broadcast signal is normally received on the basis of an operation state of the analog signal demodulation circuit in a state where an operation of the digital demodulation circuit is stopped, and for supplying the clock signal to the digital demodulation circuit when the analog broadcast signal is not normally received to supply the control signal to the PLL circuit.
2 . The broadcast signal receiver according to claim 1 , wherein the control circuit uses an AFC (Automatic Frequency Control) signal as a signal that indicates the operation state of the analog signal demodulation circuit and determines whether or not the analog broadcast signal is normally received on the basis of a comparison result after comparing an output level of the AFC signal with a reference value.
3 . The broadcast signal receiver according to claim 1 , wherein the signal transmission line passing through the digital demodulation circuit is composed of an I 2 C bus, the PLL circuit is connected to the I 2 C bus on a side of the frequency conversion circuit, and an MPEG circuit for decoding a demodulation digital signal is connected to the I 2 C bus on a side opposite to the frequency conversion circuit.