Methods for eliminating phase distortion in signals

1. A circuit comprising:

a detecting circuit comprising a first input and a second input, with a first signal received into the first input and a second signal received into the second input, wherein the detecting circuit is configured to detect a first edge of the first signal and a second edge of the second signal, and wherein the second edge immediately follows the first edge and is in a same direction as the first edge;

an output node;

a constant voltage node at a constant voltage; and

a signal regenerator connected to the detecting circuit and the output node, wherein the signal regenerator is configured to clip the constant voltage from the constant voltage node to generate an output signal having an additional first edge and an additional second edge, and wherein the additional first edge and the additional second edge are opposite edges substantially aligned to the first edge and the second edge, respectively, and wherein the additional first edge and the additional second edge are immediate neighboring edges.

2. The circuit of claim 1 , wherein the first and the second signals are complementary signals, and wherein the first and the second edges are rising edges.

3. The circuit of claim 1 , wherein the first and the second signals are complementary signals, and wherein the first and the second edges are falling edges.

4. The circuit of claim 1 , wherein the signal regenerator has a first portion combined with a first sub-circuit of the detecting circuit to form a selecting circuit, and a second portion combined with a second sub-circuit of the detecting circuit to form a resetting circuit, and wherein an output of the selecting circuit is connected to a first input of the resetting circuit.

5. The circuit of claim 4 , wherein at least one of the selecting circuit and the resetting circuit comprises a time delay device for matching delays in the selecting circuit and the resetting circuit.

6. The circuit of claim 4 , wherein the selecting circuit comprises an input connected to the first signal, and wherein the resetting circuit further comprises a second input connected to the second signal, and an output connected to the output node.

7. The circuit of claim 6 , wherein the resetting circuit is configured for passing a first portion of the constant voltage from the constant voltage node, and resetting a second portion of selected data to a signal level opposite to a signal level of the constant voltage, and wherein the selecting circuit and the resetting circuit respond to the first edge of the first signal and the second edge of the second signal.

8. A method comprising:

receiving a first signal and a second input signal at different inputs of a circuit, wherein the first and the second input signals are complementary to each other;

detecting a first edge of the first signal;

detecting a second edge of the second signal, wherein the first and the second edges are in a same direction, and wherein the second edge immediately follows the first edge; and

generating an output signal having a third and a fourth edge substantially aligned with the first and the second edges, respectively, wherein the third and the fourth edges are opposite edges immediately next to each other, wherein the step of generating the output signal comprises:

starting from the first edge, passing a constant voltage received from a constant voltage node as the output signal; and

starting from the second edge, resetting the output signal to a level opposite to the constant voltage.

9. The method of claim 8 , wherein the first and the second edges are rising edges.

10. The method of claim 8 , wherein the first and the second edges are falling edges.

11. The method of claim 8 further comprising delaying one of the steps of passing and resetting to match a passing delay and a resetting delay.