MOS solid-state image pickup device and manufacturing method thereof
View Patent ↗An N-type epitaxial layer 115 , which is formed above an N-type semiconductor substrate 114 in each of a pixel region and a peripheral circuit region; a first P-type well 1 formed above the N-type epitaxial layer 115 in the pixel region; and light receiving regions 117 , which are formed within the first P-type well 1 and each of which is a component of a photodiode, are included. The peripheral circuit region includes: second P-type wells 2 , which are formed from a surface 200 of the peripheral circuit region to a desired depth and each of which is a component of an N-Channel MOS transistor; an N-type well 3 which is formed from the surface 200 of the peripheral circuit region to a desired depth and which is a component of a P-Channel MOS transistor; and a third P-type well 4 which is formed so as to have such a shape as to isolate the N-type well 3 from the N-type epitaxial layer 115 and which has a higher impurity concentration than that of the first P-type well 1.
1. A MOS solid-state image pickup device comprising, on an N-type semiconductor substrate, a pixel region, in which a plurality of pixels are formed, and a peripheral circuit region in which a peripheral circuit of the pixel region is formed, wherein
the pixel region and the peripheral circuit region each include an N-type epitaxial layer which is formed above the N-type semiconductor substrate,
the pixel region includes:
a first P-type well formed above the N-type epitaxial layer; and
light receiving regions, which are formed within the first P-type well and each of which is a component of a photodiode, and
the peripheral circuit region includes:
second P-type wells, which are formed to a desired depth from a surface of the peripheral circuit region and each of which is a component of an N-Channel MOS transistor;
an N-type well which is formed to a desired depth from the surface of the peripheral circuit region and which is a component of a P-Channel MOS transistor; and
a third P-type well which is formed so as to have such a shape as to isolate the N-type well from the N-type epitaxial layer and which has a higher impurity concentration than that of the first P-type well.
2. The MOS solid-state image pickup device according to claim 1 , wherein
the first P-type well is a retrograde well having an impurity concentration which increases in accordance with an increase in depth from the surface of the pixel region and which is extremely high at a position deeper than that of a depletion layer generated around each light receiving region.
3. The MOS solid-state image pickup device according to claim 1 , wherein the P-Channel MOS transistor is driven by a voltage which has been boosted such that the voltage is higher than an external power supply voltage.
4. The MOS solid-state image pickup device according to claim 1 , wherein an impurity concentration of the third P-type well is no less than 10 17 /cm 3 .